mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-26 05:20:30 +00:00
D10v memory map changed. Update.
Initialize IMAP/DMAP registers to hardware reset value.
This commit is contained in:
Andrew Cagney
parent
f6826586c5
commit
8904ad6940
@ -36,7 +36,6 @@ static void do_long PARAMS ((uint32 ins));
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static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright));
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static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
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static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
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static void init_system PARAMS ((void));
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extern void sim_set_profile PARAMS ((int n));
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extern void sim_set_profile_size PARAMS ((int n));
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@ -114,7 +113,7 @@ bfd_vma
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decode_pc ()
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{
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asection *s;
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if (!init_text_p)
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if (!init_text_p && prog_bfd != NULL)
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{
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init_text_p = 1;
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for (s = prog_bfd->sections; s; s = s->next)
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@ -315,10 +314,6 @@ sim_size (power)
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exit(1);
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}
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SET_IMAP0(0x1000);
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SET_IMAP1(0x1000);
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SET_DMAP(0);
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_MEMSIZE) != 0)
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{
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@ -333,13 +328,6 @@ sim_size (power)
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#endif
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}
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static void
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init_system ()
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{
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if (!State.imem)
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sim_size(1);
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}
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/* Transfer data to/from simulated memory. Since a bug in either the
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simulated program or in gdb or the simulator itself may cause a
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bogus address to be passed in, we need to do some sanity checking
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@ -348,138 +336,159 @@ init_system ()
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than aborting the entire run. */
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static int
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xfer_mem (addr, buffer, size, write)
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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int write;
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xfer_mem (SIM_ADDR addr,
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unsigned char *buffer,
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int size,
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int write_p)
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{
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if (!State.imem)
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init_system ();
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unsigned char *memory;
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int segment = ((addr >> 24) & 0xff);
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addr = (addr & 0x00ffffff);
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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{
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if (write)
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if (write_p)
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr);
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%02x:%06x\n", size, segment, addr);
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}
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else
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr);
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%2x:%6x\n", size, segment, addr);
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}
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}
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#endif
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/* to access data, we use the following mapping
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0x00000000 - 0x00ffffff : 16 Mb of external unified memory in segments of 128 Kb each
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0x01000000 - 0x0103ffff : 256 Kb of external instruction memory
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0x02000000 - 0x0200ffff : 32 Kb of on chip data memory + 16 Kb DMAP memory + 16 Kb I/O space */
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/* to access data, we use the following mapping
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0x00xxxxxx: Logical data address segment (DMAP translated memory)
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0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
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0x10xxxxxx: Physical data memory segment (On-chip data memory)
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0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
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0x12xxxxxx: Phisical unified memory segment (Unified memory)
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*/
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if ((addr | 0x00ffffff) == 0x00ffffff)
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switch (segment)
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{
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/* UNIFIED MEMORY (0x00000000 - 0x00ffffff) */
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int startsegment, startoffset; /* Segment and offset within segment where xfer starts */
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int endsegment, endoffset; /* Segment and offset within segment where xfer ends */
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case 0x00: /* DMAP translated memory */
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{
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int byte;
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for (byte = 0; byte < size; byte++)
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{
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uint8 *mem = dmem_addr (addr + byte);
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if (mem == NULL)
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return byte;
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else if (write_p)
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*mem = buffer[byte];
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else
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buffer[byte] = *mem;
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}
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return byte;
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}
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startsegment = addr >> UMEM_SIZE;
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startoffset = addr & ((1 << UMEM_SIZE) - 1);
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endsegment = (addr + size) >> UMEM_SIZE;
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endoffset = (addr + size) & ((1 << UMEM_SIZE) - 1);
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case 0x01: /* IMAP translated memory */
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{
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int byte;
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for (byte = 0; byte < size; byte++)
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{
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uint8 *mem = imem_addr (addr + byte);
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if (mem == NULL)
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return byte;
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else if (write_p)
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*mem = buffer[byte];
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else
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buffer[byte] = *mem;
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}
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return byte;
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}
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/* FIXME: We do not currently implement xfers across segments, so detect this case and fail gracefully. */
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case 0x10: /* On-chip data memory */
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{
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addr &= ((1 << DMEM_SIZE) - 1);
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if ((addr + size) > (1 << DMEM_SIZE))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
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addr + size - 1, (1 << DMEM_SIZE) - 1);
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return (0);
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}
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memory = State.dmem + addr;
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break;
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}
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if ((startsegment != endsegment) && !((endsegment == (startsegment + 1)) && endoffset == 0))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
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return (0);
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}
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if (!State.umem[startsegment])
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{
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case 0x11: /* On-chip insn memory */
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{
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addr &= ((1 << IMEM_SIZE) - 1);
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if ((addr + size) > (1 << IMEM_SIZE))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
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addr + size - 1, (1 << IMEM_SIZE) - 1);
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return (0);
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}
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memory = State.imem + addr;
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}
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case 0x12: /* Unified memory */
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{
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int startsegment, startoffset; /* Segment and offset within segment where xfer starts */
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int endsegment, endoffset; /* Segment and offset within segment where xfer ends */
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startsegment = addr >> UMEM_SIZE;
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startoffset = addr & ((1 << UMEM_SIZE) - 1);
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endsegment = (addr + size) >> UMEM_SIZE;
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endoffset = (addr + size) & ((1 << UMEM_SIZE) - 1);
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/* FIXME: We do not currently implement xfers across segments,
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so detect this case and fail gracefully. */
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if ((startsegment != endsegment) && !((endsegment == (startsegment + 1)) && endoffset == 0))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
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return (0);
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}
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if (!State.umem[startsegment])
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{
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_MEMSIZE) != 0)
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{
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(*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n",
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add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), startsegment);
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}
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if ((d10v_debug & DEBUG_MEMSIZE) != 0)
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{
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(*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n",
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add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), startsegment);
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}
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#endif
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State.umem[startsegment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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}
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if (!State.umem[startsegment])
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE);
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return (0);
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}
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if (write)
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{
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memcpy (State.umem[startsegment]+startoffset, buffer, size);
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}
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else
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{
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memcpy (buffer, State.umem[startsegment]+startoffset, size);
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}
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State.umem[startsegment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
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}
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if (!State.umem[startsegment])
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE);
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return (0);
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}
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memory = State.umem[startsegment] + startoffset;
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break;
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}
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default:
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%lx is not in valid range\n", (long) addr);
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(*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx: Logical data address segment (DMAP translated memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx: Physical data memory segment (On-chip data memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "0x12xxxxxx: Phisical unified memory segment (Unified memory)\n");
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return (0);
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}
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}
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else if ((addr | 0x0003ffff) == 0x0103ffff)
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if (write_p)
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{
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/* INSTRUCTION MEMORY (0x01000000 - 0x0103ffff) */
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addr &= ((1 << IMEM_SIZE) - 1);
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if ((addr + size) > (1 << IMEM_SIZE))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
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addr + size - 1, (1 << IMEM_SIZE) - 1);
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return (0);
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}
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if (write)
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{
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memcpy (State.imem+addr, buffer, size);
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}
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else
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{
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memcpy (buffer, State.imem+addr, size);
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}
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}
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else if ((addr | 0x0000ffff) == 0x0200ffff)
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{
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/* DATA MEMORY (0x02000000 - 0x0200ffff) */
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addr &= ((1 << DMEM_SIZE) - 1);
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if ((addr + size) > (1 << DMEM_SIZE))
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
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addr + size - 1, (1 << DMEM_SIZE) - 1);
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return (0);
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}
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if (write)
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{
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memcpy (State.dmem+addr, buffer, size);
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}
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else
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{
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memcpy (buffer, State.dmem+addr, size);
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}
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memcpy (memory, buffer, size);
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}
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else
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr);
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(*d10v_callback->printf_filtered) (d10v_callback, "Unified memory addresses are 0x00000000 - 0x00ffffff\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses are 0x01000000 - 0x0103ffff\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "Data addresses are 0x02000000 - 0x0200ffff\n");
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return (0);
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memcpy (buffer, memory, size);
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}
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return size;
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}
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static int
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sim_write_phys (sd, addr, buffer, size)
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SIM_DESC sd;
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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{
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return xfer_mem( addr, buffer, size, 1);
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}
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int
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sim_write (sd, addr, buffer, size)
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SIM_DESC sd;
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@ -555,6 +564,11 @@ sim_open (kind, callback, abfd, argv)
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}
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}
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/* reset the processor state */
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if (!State.imem)
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sim_size(1);
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sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
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/* Fudge our descriptor. */
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return (SIM_DESC) 1;
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}
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@ -632,10 +646,9 @@ dmem_addr( addr )
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}
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static uint8 *
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pc_addr()
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uint8 *
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imem_addr (uint32 pc)
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{
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uint32 pc = ((uint32)PC) << 2;
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uint16 imap;
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if (pc & 0x20000)
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@ -647,12 +660,7 @@ pc_addr()
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return State.imem + pc;
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if (State.umem[imap & 0xff] == NULL)
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
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imap & 0xff, (long)PC);
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State.exception = SIGBUS;
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return 0;
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}
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return 0;
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/* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
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pc &= (1 << UMEM_SIZE) - 1;
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@ -680,6 +688,7 @@ sim_resume (sd, step, siggnal)
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{
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uint32 inst;
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int do_iba;
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uint8 *iaddr;
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/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
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State.exception = 0;
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@ -688,7 +697,15 @@ sim_resume (sd, step, siggnal)
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do
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{
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inst = get_longword( pc_addr() );
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iaddr = imem_addr ((uint32)PC << 2);
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if (iaddr == NULL)
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{
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State.exception = SIGBUS;
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break;
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}
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inst = get_longword( iaddr );
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State.pc_changed = 0;
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ins_type_counters[ (int)INS_CYCLES ]++;
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@ -882,6 +899,24 @@ sim_create_inferior (sd, abfd, argv, env)
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/* reset all state information */
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memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
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if (argv)
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{
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/* a hack to set r0/r1 with argc/argv */
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/* some high memory that won't be overwritten by the stack soon */
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addr = State.regs[0] = 0x7C00;
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p = 20;
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i = 0;
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while (argv[i])
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{
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SW (addr + 2*i, addr + p);
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size = strlen (argv[i]) + 1;
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sim_write (sd, addr + 0, argv[i], size);
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p += size;
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i++;
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}
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State.regs[1] = i;
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}
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/* set PC */
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if (abfd != NULL)
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start_address = bfd_get_start_address (abfd);
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@ -895,10 +930,18 @@ sim_create_inferior (sd, abfd, argv, env)
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/* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
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/* resets imap0 and imap1 to 0x1000. */
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SET_IMAP0(0x1000);
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SET_IMAP1(0x1000);
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SET_DMAP(0);
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if (1)
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{
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SET_IMAP0 (0x0000);
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SET_IMAP1 (0x007f);
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SET_DMAP (0x0000);
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}
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else
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{
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SET_IMAP0(0x1000);
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SET_IMAP1(0x1000);
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SET_DMAP(0);
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}
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return SIM_RC_OK;
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}
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@ -928,7 +971,7 @@ sim_stop_reason (sd, reason, sigrc)
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case SIG_D10V_EXIT: /* exit trap */
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*reason = sim_exited;
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*sigrc = State.regs[2];
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*sigrc = State.regs[0];
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break;
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default: /* some signal */
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@ -949,9 +992,6 @@ sim_fetch_register (sd, rn, memory)
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int rn;
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unsigned char *memory;
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{
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if (!State.imem)
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init_system();
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if (rn > 34)
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WRITE_64 (memory, State.a[rn-35]);
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else if (rn == 32)
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@ -972,9 +1012,6 @@ sim_store_register (sd, rn, memory)
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int rn;
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unsigned char *memory;
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{
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if (!State.imem)
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init_system();
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if (rn > 34)
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State.a[rn-35] = READ_64 (memory) & MASK40;
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else if (rn == 34)
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@ -1014,7 +1051,7 @@ sim_load (sd, prog, abfd, from_tty)
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}
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prog_bfd = sim_load_file (sd, myname, d10v_callback, prog, abfd,
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sim_kind == SIM_OPEN_DEBUG,
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0, sim_write_phys);
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1/*LMA*/, sim_write);
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if (prog_bfd == NULL)
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return SIM_RC_FAIL;
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prog_bfd_was_opened_p = abfd == NULL;
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