mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-23 12:09:49 +00:00
bfd/
2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_architecture): Add bfd_arch_l1om. (bfd_l1om_arch): New. (bfd_archures_list): Add &bfd_l1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. * configure: Regenerated. * cpu-l1om.c: New. * elf64-x86-64.c (elf64_l1om_elf_object_p): New. (bfd_elf64_l1om_vec): Likewise. (bfd_elf64_l1om_freebsd_vec): Likewise. * Makefile.am (ALL_MACHINES): Add cpu-l1om.lo. (ALL_MACHINES_CFILES): Add cpu-l1om.c. * Makefile.in: Regenerated. * targets.c (bfd_elf64_l1om_vec): New. (bfd_elf64_l1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. binutils/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (guess_is_rela): Handle EM_L1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. gas/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add l1om. (check_cpu_arch_compatible): New. (set_cpu_arch): Use it. (i386_arch): New. (i386_mach): Return bfd_mach_l1om for Intel L1OM. (md_show_usage): Display l1om. (i386_target_format): Return ELF_TARGET_L1OM_FORMAT if cpu_arch_isa_flags.bitfield.cpul1om is set. * config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()). (i386_arch): New. (ELF_TARGET_L1OM_FORMAT): Likewise. * doc/c-i386.texi: Document l1om. gas/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/l1om.d: New. * gas/i386/l1om-inval.l: Likewise. * gas/i386/l1om-inval.s: Likewise. * gas/i386/i386.exp: Run l1om-inval and l1om. include/elf/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_L1OM): New. ld/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64 is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and eelf_l1om_fbsd.o (eelf_l1om.c): New. (eelf_l1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * emulparams/elf_l1om.sh: New. * emulparams/elf_l1om_fbsd.sh: Likewise. ld/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-l1om.d: New. * ld-x86-64/protected2-l1om.d: Likewise. * ld-x86-64/protected3-l1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and protected3-l1om. opcodes/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_l1om_arch. * disassemble.c (disassembler): Likewise. * configure: Regenerated. * i386-dis.c (print_insn): Handle bfd_mach_l1om and bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. Add CPU_L1OM_FLAGS. (cpu_flags): Add CpuL1OM. (set_bitfield): Take an argument to set the value field. (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY). (process_i386_opcode_modifier): Updated. (process_i386_operand_type): Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuL1OM): New. (CpuXsave): Updated. (i386_cpu_flags): Add cpul1om.
This commit is contained in:
H.J. Lu
parent
bdc0e08dbc
commit
8a9036a406
@ -1,3 +1,34 @@
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2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
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* archures.c (bfd_architecture): Add bfd_arch_l1om.
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(bfd_l1om_arch): New.
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(bfd_archures_list): Add &bfd_l1om_arch.
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* bfd-in2.h: Regenerated.
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* config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if
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bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec
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if bfd_elf64_x86_64_freebsd_vec is supported.
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(targ_selvecs): Likewise.
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* configure.in: Support bfd_elf64_l1om_vec and
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bfd_elf64_l1om_freebsd_vec.
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* configure: Regenerated.
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* cpu-l1om.c: New.
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* elf64-x86-64.c (elf64_l1om_elf_object_p): New.
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(bfd_elf64_l1om_vec): Likewise.
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(bfd_elf64_l1om_freebsd_vec): Likewise.
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* Makefile.am (ALL_MACHINES): Add cpu-l1om.lo.
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(ALL_MACHINES_CFILES): Add cpu-l1om.c.
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* Makefile.in: Regenerated.
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* targets.c (bfd_elf64_l1om_vec): New.
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(bfd_elf64_l1om_freebsd_vec): Likewise.
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(_bfd_target_vector): Add bfd_elf64_l1om_vec and
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bfd_elf64_l1om_freebsd_vec.
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2009-07-24 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
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Alan Modra <amodra@bigpond.net.au>
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@ -83,6 +83,7 @@ ALL_MACHINES = \
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cpu-hppa.lo \
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cpu-i370.lo \
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cpu-i386.lo \
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cpu-l1om.lo \
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cpu-i860.lo \
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cpu-i960.lo \
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cpu-ia64.lo \
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@ -152,6 +153,7 @@ ALL_MACHINES_CFILES = \
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cpu-hppa.c \
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cpu-i370.c \
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cpu-i386.c \
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cpu-l1om.c \
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cpu-i860.c \
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cpu-i960.c \
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cpu-ia64.c \
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@ -1309,6 +1311,10 @@ cpu-i386.lo: \
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cpu-i386.c \
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$(INCDIR)/filenames.h \
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$(INCDIR)/hashtab.h
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cpu-l1om.lo: \
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cpu-l1om.c \
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$(INCDIR)/filenames.h \
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$(INCDIR)/hashtab.h
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cpu-i860.lo: \
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cpu-i860.c \
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$(INCDIR)/filenames.h \
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@ -353,6 +353,7 @@ ALL_MACHINES = \
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cpu-hppa.lo \
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cpu-i370.lo \
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cpu-i386.lo \
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cpu-l1om.lo \
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cpu-i860.lo \
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cpu-i960.lo \
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cpu-ia64.lo \
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@ -422,6 +423,7 @@ ALL_MACHINES_CFILES = \
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cpu-hppa.c \
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cpu-i370.c \
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cpu-i386.c \
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cpu-l1om.c \
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cpu-i860.c \
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cpu-i960.c \
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cpu-ia64.c \
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@ -1910,6 +1912,10 @@ cpu-i386.lo: \
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cpu-i386.c \
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$(INCDIR)/filenames.h \
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$(INCDIR)/hashtab.h
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cpu-l1om.lo: \
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cpu-l1om.c \
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$(INCDIR)/filenames.h \
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$(INCDIR)/hashtab.h
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cpu-i860.lo: \
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cpu-i860.c \
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$(INCDIR)/filenames.h \
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@ -186,6 +186,9 @@ DESCRIPTION
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.#define bfd_mach_i386_i386_intel_syntax 3
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.#define bfd_mach_x86_64 64
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.#define bfd_mach_x86_64_intel_syntax 65
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. bfd_arch_l1om, {* Intel L1OM *}
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.#define bfd_mach_l1om 66
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.#define bfd_mach_l1om_intel_syntax 67
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. bfd_arch_we32k, {* AT&T WE32xxx *}
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. bfd_arch_tahoe, {* CCI/Harris Tahoe *}
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. bfd_arch_i860, {* Intel 860 *}
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@ -476,6 +479,7 @@ extern const bfd_arch_info_type bfd_h8500_arch;
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extern const bfd_arch_info_type bfd_hppa_arch;
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extern const bfd_arch_info_type bfd_i370_arch;
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extern const bfd_arch_info_type bfd_i386_arch;
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extern const bfd_arch_info_type bfd_l1om_arch;
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extern const bfd_arch_info_type bfd_i860_arch;
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extern const bfd_arch_info_type bfd_i960_arch;
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extern const bfd_arch_info_type bfd_ia64_arch;
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@ -550,6 +554,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
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&bfd_hppa_arch,
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&bfd_i370_arch,
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&bfd_i386_arch,
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&bfd_l1om_arch,
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&bfd_i860_arch,
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&bfd_i960_arch,
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&bfd_ia64_arch,
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@ -1835,6 +1835,9 @@ enum bfd_architecture
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#define bfd_mach_i386_i386_intel_syntax 3
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#define bfd_mach_x86_64 64
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#define bfd_mach_x86_64_intel_syntax 65
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bfd_arch_l1om, /* Intel L1OM */
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#define bfd_mach_l1om 66
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#define bfd_mach_l1om_intel_syntax 67
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bfd_arch_we32k, /* AT&T WE32xxx */
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bfd_arch_tahoe, /* CCI/Harris Tahoe */
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bfd_arch_i860, /* Intel 860 */
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@ -500,13 +500,13 @@ case "${targ}" in
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i[3-7]86-*-solaris2*)
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targ_defvec=bfd_elf32_i386_vec
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targ_selvecs=i386coff_vec
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targ64_selvecs=bfd_elf64_x86_64_vec
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targ64_selvecs="bfd_elf64_x86_64_vec bfd_elf64_l1om_vec"
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want64=true
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;;
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#ifdef BFD64
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x86_64-*-solaris2*)
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targ_defvec=bfd_elf32_i386_vec
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targ_selvecs="bfd_elf64_x86_64_vec i386coff_vec"
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targ_selvecs="bfd_elf64_x86_64_vec bfd_elf64_l1om_vec i386coff_vec"
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want64=true
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;;
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#endif
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@ -526,7 +526,7 @@ case "${targ}" in
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;;
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i[3-7]86-*-dicos*)
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targ_defvec=bfd_elf32_i386_vec
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targ64_selvecs=bfd_elf64_x86_64_vec
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targ64_selvecs="bfd_elf64_x86_64_vec bfd_elf64_l1om_vec"
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;;
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*-*-msdosdjgpp* | *-*-go32* )
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targ_defvec=go32coff_vec
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@ -562,7 +562,7 @@ case "${targ}" in
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i[3-7]86-*-freebsd* | i[3-7]86-*-kfreebsd*-gnu | i[3-7]86-*-dragonfly*)
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targ_defvec=bfd_elf32_i386_freebsd_vec
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targ_selvecs="bfd_elf32_i386_vec i386pei_vec i386coff_vec"
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targ64_selvecs="bfd_elf64_x86_64_freebsd_vec bfd_elf64_x86_64_vec x86_64pei_vec"
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targ64_selvecs="bfd_elf64_x86_64_freebsd_vec bfd_elf64_x86_64_vec x86_64pei_vec bfd_elf64_l1om_vec bfd_elf64_l1om_freebsd_vec"
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# FreeBSD <= 4.0 supports only the old nonstandard way of ABI labelling.
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case "${targ}" in
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i[3-7]86-*-freebsd3* | i[3-7]86-*-freebsd4 | i[3-7]86-*-freebsd4.0*)
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@ -572,7 +572,7 @@ case "${targ}" in
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i[3-7]86-*-netbsdelf* | i[3-7]86-*-netbsd*-gnu* | i[3-7]86-*-knetbsd*-gnu)
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targ_defvec=bfd_elf32_i386_vec
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targ_selvecs=i386netbsd_vec
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targ64_selvecs=bfd_elf64_x86_64_vec
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targ64_selvecs="bfd_elf64_x86_64_vec bfd_elf64_l1om_vec"
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;;
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i[3-7]86-*-netbsdpe*)
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targ_defvec=i386pe_vec
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@ -600,7 +600,7 @@ case "${targ}" in
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i[3-7]86-*-linux-*)
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targ_defvec=bfd_elf32_i386_vec
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targ_selvecs="i386linux_vec i386pei_vec"
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targ64_selvecs=bfd_elf64_x86_64_vec
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targ64_selvecs="bfd_elf64_x86_64_vec bfd_elf64_l1om_vec"
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;;
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#ifdef BFD64
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x86_64-*-darwin*)
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@ -611,32 +611,32 @@ case "${targ}" in
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;;
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x86_64-*-dicos*)
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targ_defvec=bfd_elf64_x86_64_vec
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targ_selvecs="bfd_elf32_i386_vec"
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targ_selvecs="bfd_elf32_i386_vec bfd_elf64_l1om_vec"
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want64=true
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;;
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x86_64-*-elf*)
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targ_defvec=bfd_elf64_x86_64_vec
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targ_selvecs="bfd_elf32_i386_vec i386coff_vec"
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targ_selvecs="bfd_elf32_i386_vec bfd_elf64_l1om_vec i386coff_vec"
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want64=true
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;;
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x86_64-*-freebsd* | x86_64-*-kfreebsd*-gnu)
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targ_defvec=bfd_elf64_x86_64_freebsd_vec
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targ_selvecs="bfd_elf32_i386_freebsd_vec i386coff_vec i386pei_vec x86_64pei_vec bfd_elf32_i386_vec bfd_elf64_x86_64_vec"
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targ_selvecs="bfd_elf32_i386_freebsd_vec i386coff_vec i386pei_vec x86_64pei_vec bfd_elf32_i386_vec bfd_elf64_x86_64_vec bfd_elf64_l1om_vec bfd_elf64_l1om_freebsd_vec"
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want64=true
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;;
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x86_64-*-netbsd* | x86_64-*-openbsd*)
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targ_defvec=bfd_elf64_x86_64_vec
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targ_selvecs="bfd_elf32_i386_vec i386netbsd_vec i386coff_vec i386pei_vec x86_64pei_vec"
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targ_selvecs="bfd_elf32_i386_vec i386netbsd_vec i386coff_vec i386pei_vec x86_64pei_vec bfd_elf64_l1om_vec"
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want64=true
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;;
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x86_64-*-linux-*)
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targ_defvec=bfd_elf64_x86_64_vec
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targ_selvecs="bfd_elf32_i386_vec i386linux_vec i386pei_vec x86_64pei_vec"
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targ_selvecs="bfd_elf32_i386_vec i386linux_vec i386pei_vec x86_64pei_vec bfd_elf64_l1om_vec"
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want64=true
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;;
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x86_64-*-mingw*)
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targ_defvec=x86_64pe_vec
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targ_selvecs="x86_64pe_vec x86_64pei_vec bfd_elf64_x86_64_vec"
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targ_selvecs="x86_64pe_vec x86_64pei_vec bfd_elf64_x86_64_vec bfd_elf64_l1om_vec"
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want64=true
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targ_underscore=yes
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;;
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@ -1573,3 +1573,10 @@ case "${targ_defvec} ${targ_selvecs}" in
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targ_selvecs="${targ_selvecs} bfd_elf32_little_generic_vec bfd_elf32_big_generic_vec"
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;;
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esac
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# If we support Intel L1OM target, then add support for bfd_l1om_arch.
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case "${targ_defvec} ${targ_selvecs}" in
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*bfd_elf64_l1om_vec*)
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targ_archs="$targ_archs bfd_l1om_arch"
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;;
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esac
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2
bfd/configure
vendored
2
bfd/configure
vendored
@ -21323,6 +21323,8 @@ do
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bfd_elf64_tradlittlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
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bfd_elf64_x86_64_freebsd_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_elf64_x86_64_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_elf64_l1om_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_elf64_l1om_freebsd_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_mmo_vec) tb="$tb mmo.lo" target_size=64 ;;
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bfd_powerpc_pe_vec) tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;;
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bfd_powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
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@ -827,6 +827,8 @@ do
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bfd_elf64_tradlittlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
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bfd_elf64_x86_64_freebsd_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_elf64_x86_64_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_elf64_l1om_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_elf64_l1om_freebsd_vec) tb="$tb elf64-x86-64.lo elf64.lo $elf"; target_size=64 ;;
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bfd_mmo_vec) tb="$tb mmo.lo" target_size=64 ;;
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bfd_powerpc_pe_vec) tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;;
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bfd_powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
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56
bfd/cpu-l1om.c
Normal file
56
bfd/cpu-l1om.c
Normal file
@ -0,0 +1,56 @@
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/* BFD support for the Intel L1OM architecture.
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Copyright 2009
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Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#include "sysdep.h"
|
||||
#include "bfd.h"
|
||||
#include "libbfd.h"
|
||||
|
||||
static const bfd_arch_info_type bfd_l1om_arch_intel_syntax =
|
||||
{
|
||||
64, /* 64 bits in a word */
|
||||
64, /* 64 bits in an address */
|
||||
8, /* 8 bits in a byte */
|
||||
bfd_arch_l1om,
|
||||
bfd_mach_l1om_intel_syntax,
|
||||
"l1om:intel",
|
||||
"l1om:intel",
|
||||
3,
|
||||
TRUE,
|
||||
bfd_default_compatible,
|
||||
bfd_default_scan,
|
||||
0
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_l1om_arch =
|
||||
{
|
||||
64, /* 32 bits in a word */
|
||||
64, /* 32 bits in an address */
|
||||
8, /* 8 bits in a byte */
|
||||
bfd_arch_l1om,
|
||||
bfd_mach_l1om,
|
||||
"l1om",
|
||||
"l1om",
|
||||
3,
|
||||
TRUE,
|
||||
bfd_default_compatible,
|
||||
bfd_default_scan,
|
||||
&bfd_l1om_arch_intel_syntax
|
||||
};
|
||||
@ -4483,3 +4483,53 @@ static const struct bfd_elf_special_section
|
||||
#define elf64_bed elf64_x86_64_fbsd_bed
|
||||
|
||||
#include "elf64-target.h"
|
||||
|
||||
/* Intel L1OM support. */
|
||||
|
||||
static bfd_boolean
|
||||
elf64_l1om_elf_object_p (bfd *abfd)
|
||||
{
|
||||
/* Set the right machine number for an L1OM elf64 file. */
|
||||
bfd_default_set_arch_mach (abfd, bfd_arch_l1om, bfd_mach_l1om);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
#undef TARGET_LITTLE_SYM
|
||||
#define TARGET_LITTLE_SYM bfd_elf64_l1om_vec
|
||||
#undef TARGET_LITTLE_NAME
|
||||
#define TARGET_LITTLE_NAME "elf64-l1om"
|
||||
#undef ELF_ARCH
|
||||
#define ELF_ARCH bfd_arch_l1om
|
||||
|
||||
#undef ELF_MACHINE_CODE
|
||||
#define ELF_MACHINE_CODE EM_L1OM
|
||||
|
||||
#undef ELF_OSABI
|
||||
|
||||
#undef elf64_bed
|
||||
#define elf64_bed elf64_l1om_bed
|
||||
|
||||
#undef elf_backend_object_p
|
||||
#define elf_backend_object_p elf64_l1om_elf_object_p
|
||||
|
||||
#undef elf_backend_post_process_headers
|
||||
|
||||
#include "elf64-target.h"
|
||||
|
||||
/* FreeBSD L1OM support. */
|
||||
|
||||
#undef TARGET_LITTLE_SYM
|
||||
#define TARGET_LITTLE_SYM bfd_elf64_l1om_freebsd_vec
|
||||
#undef TARGET_LITTLE_NAME
|
||||
#define TARGET_LITTLE_NAME "elf64-l1om-freebsd"
|
||||
|
||||
#undef ELF_OSABI
|
||||
#define ELF_OSABI ELFOSABI_FREEBSD
|
||||
|
||||
#undef elf64_bed
|
||||
#define elf64_bed elf64_l1om_fbsd_bed
|
||||
|
||||
#undef elf_backend_post_process_headers
|
||||
#define elf_backend_post_process_headers _bfd_elf_set_osabi
|
||||
|
||||
#include "elf64-target.h"
|
||||
|
||||
@ -698,6 +698,8 @@ extern const bfd_target bfd_elf64_tradbigmips_vec;
|
||||
extern const bfd_target bfd_elf64_tradlittlemips_vec;
|
||||
extern const bfd_target bfd_elf64_x86_64_freebsd_vec;
|
||||
extern const bfd_target bfd_elf64_x86_64_vec;
|
||||
extern const bfd_target bfd_elf64_l1om_freebsd_vec;
|
||||
extern const bfd_target bfd_elf64_l1om_vec;
|
||||
extern const bfd_target bfd_mmo_vec;
|
||||
extern const bfd_target bfd_powerpc_pe_vec;
|
||||
extern const bfd_target bfd_powerpc_pei_vec;
|
||||
@ -1037,6 +1039,8 @@ static const bfd_target * const _bfd_target_vector[] =
|
||||
&bfd_elf64_tradlittlemips_vec,
|
||||
&bfd_elf64_x86_64_freebsd_vec,
|
||||
&bfd_elf64_x86_64_vec,
|
||||
&bfd_elf64_l1om_freebsd_vec,
|
||||
&bfd_elf64_l1om_vec,
|
||||
&bfd_mmo_vec,
|
||||
#endif
|
||||
&bfd_powerpc_pe_vec,
|
||||
|
||||
@ -1,3 +1,17 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* readelf.c (guess_is_rela): Handle EM_L1OM.
|
||||
(dump_relocations): Likewise.
|
||||
(get_machine_name): Likewise.
|
||||
(get_section_type_name): Likewise.
|
||||
(get_elf_section_flags): Likewise.
|
||||
(get_symbol_index_type): Likewise.
|
||||
(is_32bit_abs_reloc): Likewise.
|
||||
(is_32bit_pcrel_reloc): Likewise.
|
||||
(is_64bit_abs_reloc): Likewise.
|
||||
(is_64bit_pcrel_reloc): Likewise.
|
||||
(is_none_reloc): Likewise.
|
||||
|
||||
2009-07-23 Ulrich Drepper <drepper@redhat.com>
|
||||
|
||||
* readelf.c (get_symbol_binding): For Linux targeted files return
|
||||
|
||||
@ -610,6 +610,7 @@ guess_is_rela (unsigned int e_machine)
|
||||
case EM_CYGNUS_V850:
|
||||
case EM_VAX:
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
case EM_XSTORMY16:
|
||||
case EM_XTENSA:
|
||||
case EM_XTENSA_OLD:
|
||||
@ -1128,6 +1129,7 @@ dump_relocations (FILE * file,
|
||||
break;
|
||||
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
rtype = elf_x86_64_reloc_type (type);
|
||||
break;
|
||||
|
||||
@ -1292,7 +1294,8 @@ dump_relocations (FILE * file,
|
||||
else if (elf_header.e_machine == EM_MIPS
|
||||
&& psym->st_shndx == SHN_MIPS_SUNDEFINED)
|
||||
sec_name = "SUNDEF";
|
||||
else if (elf_header.e_machine == EM_X86_64
|
||||
else if ((elf_header.e_machine == EM_X86_64
|
||||
|| elf_header.e_machine == EM_L1OM)
|
||||
&& psym->st_shndx == SHN_X86_64_LCOMMON)
|
||||
sec_name = "LARGE_COMMON";
|
||||
else if (elf_header.e_machine == EM_IA_64
|
||||
@ -1837,6 +1840,7 @@ get_machine_name (unsigned e_machine)
|
||||
case EM_HUANY: return "Harvard Universitys's machine-independent object format";
|
||||
case EM_PRISM: return "Vitesse Prism";
|
||||
case EM_X86_64: return "Advanced Micro Devices X86-64";
|
||||
case EM_L1OM: return "Intel L1OM";
|
||||
case EM_S390_OLD:
|
||||
case EM_S390: return "IBM S/390";
|
||||
case EM_SCORE: return "SUNPLUS S+Core";
|
||||
@ -2776,6 +2780,7 @@ get_section_type_name (unsigned int sh_type)
|
||||
result = get_ia64_section_type_name (sh_type);
|
||||
break;
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
result = get_x86_64_section_type_name (sh_type);
|
||||
break;
|
||||
case EM_ARM:
|
||||
@ -3967,7 +3972,8 @@ get_elf_section_flags (bfd_vma sh_flags)
|
||||
case SHF_TLS: *p = 'T'; break;
|
||||
|
||||
default:
|
||||
if (elf_header.e_machine == EM_X86_64
|
||||
if ((elf_header.e_machine == EM_X86_64
|
||||
|| elf_header.e_machine == EM_L1OM)
|
||||
&& flag == SHF_X86_64_LARGE)
|
||||
*p = 'l';
|
||||
else if (flag & SHF_MASKOS)
|
||||
@ -7035,7 +7041,8 @@ get_symbol_index_type (unsigned int type)
|
||||
&& elf_header.e_machine == EM_IA_64
|
||||
&& elf_header.e_ident[EI_OSABI] == ELFOSABI_HPUX)
|
||||
return "ANSI_COM";
|
||||
else if (elf_header.e_machine == EM_X86_64
|
||||
else if ((elf_header.e_machine == EM_X86_64
|
||||
|| elf_header.e_machine == EM_L1OM)
|
||||
&& type == SHN_X86_64_LCOMMON)
|
||||
return "LARGE_COM";
|
||||
else if (type == SHN_MIPS_SCOMMON
|
||||
@ -7953,6 +7960,7 @@ is_32bit_abs_reloc (unsigned int reloc_type)
|
||||
case EM_VAX:
|
||||
return reloc_type == 1; /* R_VAX_32. */
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
return reloc_type == 10; /* R_X86_64_32. */
|
||||
case EM_XSTORMY16:
|
||||
return reloc_type == 1; /* R_XSTROMY16_32. */
|
||||
@ -8002,6 +8010,7 @@ is_32bit_pcrel_reloc (unsigned int reloc_type)
|
||||
case EM_SPU:
|
||||
return reloc_type == 13; /* R_SPU_REL32. */
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
return reloc_type == 2; /* R_X86_64_PC32. */
|
||||
case EM_XTENSA_OLD:
|
||||
case EM_XTENSA:
|
||||
@ -8037,6 +8046,7 @@ is_64bit_abs_reloc (unsigned int reloc_type)
|
||||
case EM_SPARC:
|
||||
return reloc_type == 54; /* R_SPARC_UA64. */
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
return reloc_type == 1; /* R_X86_64_64. */
|
||||
case EM_S390_OLD:
|
||||
case EM_S390:
|
||||
@ -8069,6 +8079,7 @@ is_64bit_pcrel_reloc (unsigned int reloc_type)
|
||||
case EM_SPARC:
|
||||
return reloc_type == 46; /* R_SPARC_DISP64 */
|
||||
case EM_X86_64:
|
||||
case EM_L1OM:
|
||||
return reloc_type == 24; /* R_X86_64_PC64 */
|
||||
case EM_S390_OLD:
|
||||
case EM_S390:
|
||||
@ -8138,6 +8149,7 @@ is_none_reloc (unsigned int reloc_type)
|
||||
case EM_S390: /* R_390_NONE. */
|
||||
case EM_CRIS: /* R_CRIS_NONE. */
|
||||
case EM_X86_64: /* R_X86_64_NONE. */
|
||||
case EM_L1OM: /* R_X86_64_NONE. */
|
||||
case EM_MN10300: /* R_MN10300_NONE. */
|
||||
case EM_M32R: /* R_M32R_NONE. */
|
||||
return reloc_type == 0;
|
||||
|
||||
@ -1,3 +1,20 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* config/tc-i386.c (cpu_arch): Add l1om.
|
||||
(check_cpu_arch_compatible): New.
|
||||
(set_cpu_arch): Use it.
|
||||
(i386_arch): New.
|
||||
(i386_mach): Return bfd_mach_l1om for Intel L1OM.
|
||||
(md_show_usage): Display l1om.
|
||||
(i386_target_format): Return ELF_TARGET_L1OM_FORMAT if
|
||||
cpu_arch_isa_flags.bitfield.cpul1om is set.
|
||||
|
||||
* config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()).
|
||||
(i386_arch): New.
|
||||
(ELF_TARGET_L1OM_FORMAT): Likewise.
|
||||
|
||||
* doc/c-i386.texi: Document l1om.
|
||||
|
||||
2009-07-24 Roland McGrath <roland@redhat.com>
|
||||
Mark Wielaard <mjw@redhat.com>
|
||||
|
||||
|
||||
@ -577,6 +577,8 @@ static const arch_entry cpu_arch[] =
|
||||
CPU_CORE2_FLAGS },
|
||||
{ "corei7", PROCESSOR_COREI7,
|
||||
CPU_COREI7_FLAGS },
|
||||
{ "l1om", PROCESSOR_GENERIC64,
|
||||
CPU_L1OM_FLAGS },
|
||||
{ "k6", PROCESSOR_K6,
|
||||
CPU_K6_FLAGS },
|
||||
{ "k6_2", PROCESSOR_K6,
|
||||
@ -1955,6 +1957,35 @@ set_sse_check (int dummy ATTRIBUTE_UNUSED)
|
||||
demand_empty_rest_of_line ();
|
||||
}
|
||||
|
||||
static void
|
||||
check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
|
||||
i386_cpu_flags new ATTRIBUTE_UNUSED)
|
||||
{
|
||||
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
|
||||
static const char *arch;
|
||||
|
||||
/* Intel LIOM is only supported on ELF. */
|
||||
if (!IS_ELF)
|
||||
return;
|
||||
|
||||
if (!arch)
|
||||
{
|
||||
/* Use cpu_arch_name if it is set in md_parse_option. Otherwise
|
||||
use default_arch. */
|
||||
arch = cpu_arch_name;
|
||||
if (!arch)
|
||||
arch = default_arch;
|
||||
}
|
||||
|
||||
/* If we are targeting Intel L1OM, wm must enable it. */
|
||||
if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
|
||||
|| new.bitfield.cpul1om)
|
||||
return;
|
||||
|
||||
as_bad (_("`%s' is not supported on `%s'"), name, arch);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
|
||||
{
|
||||
@ -1971,6 +2002,8 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (strcmp (string, cpu_arch[i].name) == 0)
|
||||
{
|
||||
check_cpu_arch_compatible (string, cpu_arch[i].flags);
|
||||
|
||||
if (*string != '.')
|
||||
{
|
||||
cpu_arch_name = cpu_arch[i].name;
|
||||
@ -2049,11 +2082,34 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
|
||||
demand_empty_rest_of_line ();
|
||||
}
|
||||
|
||||
enum bfd_architecture
|
||||
i386_arch (void)
|
||||
{
|
||||
if (cpu_arch_isa_flags.bitfield.cpul1om)
|
||||
{
|
||||
if (OUTPUT_FLAVOR != bfd_target_elf_flavour
|
||||
|| flag_code != CODE_64BIT)
|
||||
as_fatal (_("Intel L1OM is 64bit ELF only"));
|
||||
return bfd_arch_l1om;
|
||||
}
|
||||
else
|
||||
return bfd_arch_i386;
|
||||
}
|
||||
|
||||
unsigned long
|
||||
i386_mach ()
|
||||
{
|
||||
if (!strcmp (default_arch, "x86_64"))
|
||||
return bfd_mach_x86_64;
|
||||
{
|
||||
if (cpu_arch_isa_flags.bitfield.cpul1om)
|
||||
{
|
||||
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
|
||||
as_fatal (_("Intel L1OM is 64bit ELF only"));
|
||||
return bfd_mach_l1om;
|
||||
}
|
||||
else
|
||||
return bfd_mach_x86_64;
|
||||
}
|
||||
else if (!strcmp (default_arch, "i386"))
|
||||
return bfd_mach_i386_i386;
|
||||
else
|
||||
@ -7936,8 +7992,8 @@ md_show_usage (stream)
|
||||
generate code for CPU and EXTENSION, CPU is one of:\n\
|
||||
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
|
||||
pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
|
||||
core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
|
||||
generic32, generic64\n\
|
||||
core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
|
||||
amdfam10, generic32, generic64\n\
|
||||
EXTENSION is combination of:\n\
|
||||
8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
|
||||
ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
|
||||
@ -7948,8 +8004,8 @@ md_show_usage (stream)
|
||||
-mtune=CPU optimize for CPU, CPU is one of:\n\
|
||||
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
|
||||
pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
|
||||
core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
|
||||
generic32, generic64\n"));
|
||||
core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
|
||||
amdfam10, generic32, generic64\n"));
|
||||
fprintf (stream, _("\
|
||||
-msse2avx encode SSE instructions with VEX prefix\n"));
|
||||
fprintf (stream, _("\
|
||||
@ -8047,7 +8103,15 @@ i386_target_format (void)
|
||||
object_64bit = 1;
|
||||
use_rela_relocations = 1;
|
||||
}
|
||||
return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
|
||||
if (cpu_arch_isa_flags.bitfield.cpul1om)
|
||||
{
|
||||
if (flag_code != CODE_64BIT)
|
||||
as_fatal (_("Intel L1OM is 64bit only"));
|
||||
return ELF_TARGET_L1OM_FORMAT;
|
||||
}
|
||||
else
|
||||
return (flag_code == CODE_64BIT
|
||||
? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
|
||||
}
|
||||
#endif
|
||||
#if defined (OBJ_MACH_O)
|
||||
|
||||
@ -29,8 +29,9 @@ struct fix;
|
||||
|
||||
#define TARGET_BYTES_BIG_ENDIAN 0
|
||||
|
||||
#define TARGET_ARCH bfd_arch_i386
|
||||
#define TARGET_ARCH (i386_arch ())
|
||||
#define TARGET_MACH (i386_mach ())
|
||||
extern enum bfd_architecture i386_arch (void);
|
||||
extern unsigned long i386_mach (void);
|
||||
|
||||
#ifdef TE_FreeBSD
|
||||
@ -70,6 +71,10 @@ extern unsigned long i386_mach (void);
|
||||
#define ELF_TARGET_FORMAT64 "elf64-x86-64"
|
||||
#endif
|
||||
|
||||
#ifndef ELF_TARGET_L1OM_FORMAT
|
||||
#define ELF_TARGET_L1OM_FORMAT "elf64-l1om"
|
||||
#endif
|
||||
|
||||
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
|
||||
|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
|
||||
|| defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
|
||||
|
||||
@ -101,6 +101,7 @@ processor names are recognized:
|
||||
@code{core},
|
||||
@code{core2},
|
||||
@code{corei7},
|
||||
@code{l1om},
|
||||
@code{k6},
|
||||
@code{k6_2},
|
||||
@code{athlon},
|
||||
@ -885,7 +886,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
|
||||
@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
|
||||
@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
|
||||
@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
|
||||
@item @samp{corei7}
|
||||
@item @samp{corei7} @tab @samp{l1om}
|
||||
@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
|
||||
@item @samp{amdfam10}
|
||||
@item @samp{generic32} @tab @samp{generic64}
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* gas/i386/l1om.d: New.
|
||||
* gas/i386/l1om-inval.l: Likewise.
|
||||
* gas/i386/l1om-inval.s: Likewise.
|
||||
|
||||
* gas/i386/i386.exp: Run l1om-inval and l1om.
|
||||
|
||||
2009-07-24 Jan Beulich <jbeulich@novell.com>
|
||||
|
||||
* gas/i386/8087.[ds]: New.
|
||||
|
||||
@ -189,6 +189,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
||||
run_list_test "inval-equ-1" "-al"
|
||||
run_list_test "inval-equ-2" "-al"
|
||||
run_dump_test "ifunc"
|
||||
run_list_test "l1om-inval" "-march=l1om --32"
|
||||
}
|
||||
|
||||
# This is a PE specific test.
|
||||
@ -346,6 +347,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
||||
run_list_test "reloc64" "--defsym _bad_=1"
|
||||
run_dump_test "mixed-mode-reloc64"
|
||||
run_dump_test "x86-64-ifunc"
|
||||
run_dump_test "l1om"
|
||||
}
|
||||
|
||||
set ASFLAGS "$old_ASFLAGS"
|
||||
|
||||
2
gas/testsuite/gas/i386/l1om-inval.l
Normal file
2
gas/testsuite/gas/i386/l1om-inval.l
Normal file
@ -0,0 +1,2 @@
|
||||
Assembler messages:
|
||||
Fatal error: Intel L1OM is 64bit only
|
||||
2
gas/testsuite/gas/i386/l1om-inval.s
Normal file
2
gas/testsuite/gas/i386/l1om-inval.s
Normal file
@ -0,0 +1,2 @@
|
||||
.text
|
||||
nop
|
||||
258
gas/testsuite/gas/i386/l1om.d
Normal file
258
gas/testsuite/gas/i386/l1om.d
Normal file
@ -0,0 +1,258 @@
|
||||
#source: x86_64.s
|
||||
#as: -J -march=l1om
|
||||
#objdump: -dw --insn-width=7
|
||||
#name: l1om
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.*>:
|
||||
[ ]*[a-f0-9]+: 01 ca add %ecx,%edx
|
||||
[ ]*[a-f0-9]+: 44 01 ca add %r9d,%edx
|
||||
[ ]*[a-f0-9]+: 41 01 ca add %ecx,%r10d
|
||||
[ ]*[a-f0-9]+: 48 01 ca add %rcx,%rdx
|
||||
[ ]*[a-f0-9]+: 4d 01 ca add %r9,%r10
|
||||
[ ]*[a-f0-9]+: 41 01 c0 add %eax,%r8d
|
||||
[ ]*[a-f0-9]+: 66 41 01 c0 add %ax,%r8w
|
||||
[ ]*[a-f0-9]+: 49 01 c0 add %rax,%r8
|
||||
[ ]*[a-f0-9]+: 05 11 22 33 44 add \$0x44332211,%eax
|
||||
[ ]*[a-f0-9]+: 48 05 11 22 33 f4 add \$0xfffffffff4332211,%rax
|
||||
[ ]*[a-f0-9]+: 66 05 33 44 add \$0x4433,%ax
|
||||
[ ]*[a-f0-9]+: 48 05 11 22 33 44 add \$0x44332211,%rax
|
||||
[ ]*[a-f0-9]+: 00 ca add %cl,%dl
|
||||
[ ]*[a-f0-9]+: 00 f7 add %dh,%bh
|
||||
[ ]*[a-f0-9]+: 40 00 f7 add %sil,%dil
|
||||
[ ]*[a-f0-9]+: 41 00 f7 add %sil,%r15b
|
||||
[ ]*[a-f0-9]+: 44 00 f7 add %r14b,%dil
|
||||
[ ]*[a-f0-9]+: 45 00 f7 add %r14b,%r15b
|
||||
[ ]*[a-f0-9]+: 50 push %rax
|
||||
[ ]*[a-f0-9]+: 41 50 push %r8
|
||||
[ ]*[a-f0-9]+: 41 59 pop %r9
|
||||
[ ]*[a-f0-9]+: 04 11 add \$0x11,%al
|
||||
[ ]*[a-f0-9]+: 80 c4 11 add \$0x11,%ah
|
||||
[ ]*[a-f0-9]+: 40 80 c4 11 add \$0x11,%spl
|
||||
[ ]*[a-f0-9]+: 41 80 c0 11 add \$0x11,%r8b
|
||||
[ ]*[a-f0-9]+: 41 80 c4 11 add \$0x11,%r12b
|
||||
[ ]*[a-f0-9]+: 0f 20 c0 mov %cr0,%rax
|
||||
[ ]*[a-f0-9]+: 41 0f 20 c0 mov %cr0,%r8
|
||||
[ ]*[a-f0-9]+: 44 0f 20 c0 mov %cr8,%rax
|
||||
[ ]*[a-f0-9]+: 44 0f 22 c0 mov %rax,%cr8
|
||||
[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 66 f3 a5 rep movsw %ds:\(%rsi\),%es:\(%rdi\)
|
||||
[ ]*[a-f0-9]+: f3 48 a5 rep movsq %ds:\(%rsi\),%es:\(%rdi\)
|
||||
[ ]*[a-f0-9]+: b0 11 mov \$0x11,%al
|
||||
[ ]*[a-f0-9]+: b4 11 mov \$0x11,%ah
|
||||
[ ]*[a-f0-9]+: 40 b4 11 mov \$0x11,%spl
|
||||
[ ]*[a-f0-9]+: 41 b4 11 mov \$0x11,%r12b
|
||||
[ ]*[a-f0-9]+: b8 44 33 22 11 mov \$0x11223344,%eax
|
||||
[ ]*[a-f0-9]+: 41 b8 44 33 22 11 mov \$0x11223344,%r8d
|
||||
[ ]*[a-f0-9]+: 48 b8 88 77 66 55 44 33 22 11 mov \$0x1122334455667788,%rax
|
||||
[ ]*[a-f0-9]+: 49 b8 88 77 66 55 44 33 22 11 mov \$0x1122334455667788,%r8
|
||||
[ ]*[a-f0-9]+: 03 00 add \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 41 03 00 add \(%r8\),%eax
|
||||
[ ]*[a-f0-9]+: 45 03 00 add \(%r8\),%r8d
|
||||
[ ]*[a-f0-9]+: 49 03 00 add \(%r8\),%rax
|
||||
[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220c4>
|
||||
[ ]*[a-f0-9]+: 03 45 00 add 0x0\(%rbp\),%eax
|
||||
[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add 0x22222222,%eax
|
||||
[ ]*[a-f0-9]+: 41 03 45 00 add 0x0\(%r13\),%eax
|
||||
[ ]*[a-f0-9]+: 03 04 80 add \(%rax,%rax,4\),%eax
|
||||
[ ]*[a-f0-9]+: 41 03 04 80 add \(%r8,%rax,4\),%eax
|
||||
[ ]*[a-f0-9]+: 45 03 04 80 add \(%r8,%rax,4\),%r8d
|
||||
[ ]*[a-f0-9]+: 43 03 04 80 add \(%r8,%r8,4\),%eax
|
||||
[ ]*[a-f0-9]+: 46 01 04 81 add %r8d,\(%rcx,%r8,4\)
|
||||
[ ]*[a-f0-9]+: 03 14 c0 add \(%rax,%rax,8\),%edx
|
||||
[ ]*[a-f0-9]+: 03 14 c8 add \(%rax,%rcx,8\),%edx
|
||||
[ ]*[a-f0-9]+: 03 14 d0 add \(%rax,%rdx,8\),%edx
|
||||
[ ]*[a-f0-9]+: 03 14 d8 add \(%rax,%rbx,8\),%edx
|
||||
[ ]*[a-f0-9]+: 03 10 add \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 03 14 e8 add \(%rax,%rbp,8\),%edx
|
||||
[ ]*[a-f0-9]+: 03 14 f0 add \(%rax,%rsi,8\),%edx
|
||||
[ ]*[a-f0-9]+: 03 14 f8 add \(%rax,%rdi,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 c0 add \(%rax,%r8,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 c8 add \(%rax,%r9,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 d0 add \(%rax,%r10,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 d8 add \(%rax,%r11,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 e0 add \(%rax,%r12,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 e8 add \(%rax,%r13,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 f0 add \(%rax,%r14,8\),%edx
|
||||
[ ]*[a-f0-9]+: 42 03 14 f8 add \(%rax,%r15,8\),%edx
|
||||
[ ]*[a-f0-9]+: 83 c1 11 add \$0x11,%ecx
|
||||
[ ]*[a-f0-9]+: 83 00 11 addl \$0x11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 83 00 11 addq \$0x11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 83 00 11 addl \$0x11,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 83 04 81 11 addl \$0x11,\(%rcx,%rax,4\)
|
||||
[ ]*[a-f0-9]+: 41 83 04 81 11 addl \$0x11,\(%r9,%rax,4\)
|
||||
[ ]*[a-f0-9]+: 42 83 04 81 11 addl \$0x11,\(%rcx,%r8,4\)
|
||||
[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x2222213f>
|
||||
[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222147>
|
||||
[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222151>
|
||||
[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222215c>
|
||||
[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 addl \$0x33,0x22222222\(,%rax,8\)
|
||||
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
|
||||
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 83 04 e8 33 addl \$0x33,\(%r8,%rbp,8\)
|
||||
[ ]*[a-f0-9]+: 83 04 25 22 22 22 22 33 addl \$0x33,0x22222222
|
||||
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%al
|
||||
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%eax
|
||||
[ ]*[a-f0-9]+: a2 11 22 33 44 55 66 77 88 mov %al,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: a3 11 22 33 44 55 66 77 88 mov %eax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 48 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%rax
|
||||
[ ]*[a-f0-9]+: 48 a3 11 22 33 44 55 66 77 88 mov %rax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 48 99 cqto
|
||||
[ ]*[a-f0-9]+: 48 98 cltq
|
||||
[ ]*[a-f0-9]+: 48 63 c0 movslq %eax,%rax
|
||||
[ ]*[a-f0-9]+: 48 0f bf c0 movswq %ax,%rax
|
||||
[ ]*[a-f0-9]+: 48 0f be c0 movsbq %al,%rax
|
||||
|
||||
0+1a7 <bar>:
|
||||
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
|
||||
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
|
||||
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
|
||||
[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax
|
||||
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 mov 0x0,%eax
|
||||
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
|
||||
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1d5 <bar\+0x2e>
|
||||
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
|
||||
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
|
||||
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
|
||||
[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax
|
||||
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 mov 0x0,%eax
|
||||
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
|
||||
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 203 <foo>
|
||||
|
||||
0+203 <foo>:
|
||||
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%al
|
||||
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%ax
|
||||
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%eax
|
||||
[ ]*[a-f0-9]+: 48 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%rax
|
||||
[ ]*[a-f0-9]+: a2 11 22 33 44 55 66 77 88 mov %al,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 66 a3 11 22 33 44 55 66 77 88 mov %ax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: a3 11 22 33 44 55 66 77 88 mov %eax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 48 a3 11 22 33 44 55 66 77 88 mov %rax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%al
|
||||
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%ax
|
||||
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%eax
|
||||
[ ]*[a-f0-9]+: 48 a1 11 22 33 44 55 66 77 88 mov 0x8877665544332211,%rax
|
||||
[ ]*[a-f0-9]+: a2 11 22 33 44 55 66 77 88 mov %al,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 66 a3 11 22 33 44 55 66 77 88 mov %ax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: a3 11 22 33 44 55 66 77 88 mov %eax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 48 a3 11 22 33 44 55 66 77 88 mov %rax,0x8877665544332211
|
||||
[ ]*[a-f0-9]+: 8a 04 25 11 22 33 ff mov 0xffffffffff332211,%al
|
||||
[ ]*[a-f0-9]+: 66 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%ax
|
||||
[ ]*[a-f0-9]+: 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%eax
|
||||
[ ]*[a-f0-9]+: 48 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%rax
|
||||
[ ]*[a-f0-9]+: 88 04 25 11 22 33 ff mov %al,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 66 89 04 25 11 22 33 ff mov %ax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 89 04 25 11 22 33 ff mov %eax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 48 89 04 25 11 22 33 ff mov %rax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 8a 04 25 11 22 33 ff mov 0xffffffffff332211,%al
|
||||
[ ]*[a-f0-9]+: 66 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%ax
|
||||
[ ]*[a-f0-9]+: 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%eax
|
||||
[ ]*[a-f0-9]+: 48 8b 04 25 11 22 33 ff mov 0xffffffffff332211,%rax
|
||||
[ ]*[a-f0-9]+: 88 04 25 11 22 33 ff mov %al,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 66 89 04 25 11 22 33 ff mov %ax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 89 04 25 11 22 33 ff mov %eax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 48 89 04 25 11 22 33 ff mov %rax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: f3 0f 7e 0c 24 movq \(%rsp\),%xmm1
|
||||
[ ]*[a-f0-9]+: f3 0f 7e 0c 24 movq \(%rsp\),%xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f d6 0c 24 movq %xmm1,\(%rsp\)
|
||||
[ ]*[a-f0-9]+: 66 0f d6 0c 24 movq %xmm1,\(%rsp\)
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: df e0 fnstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
|
||||
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
|
||||
[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
|
||||
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
|
||||
[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 0f bf 00 movswl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 48 0f bf 00 movswq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
|
||||
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 48 0f b7 00 movzwq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
|
||||
#pass
|
||||
@ -1,3 +1,7 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* common.h (EM_L1OM): New.
|
||||
|
||||
2009-07-24 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
|
||||
Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
|
||||
@ -238,7 +238,7 @@
|
||||
#define EM_CR16 177 /* National Semiconductor CompactRISC 16-bit processor */
|
||||
#define EM_ETPU 178 /* Freescale Extended Time Processing Unit */
|
||||
#define EM_SLE9X 179 /* Infineon Technologies SLE9X core */
|
||||
#define EM_INTEL180 180 /* Reserved by Intel */
|
||||
#define EM_L1OM 180 /* Intel L1OM */
|
||||
#define EM_INTEL181 181 /* Reserved by Intel */
|
||||
#define EM_INTEL182 182 /* Reserved by Intel */
|
||||
|
||||
|
||||
15
ld/ChangeLog
15
ld/ChangeLog
@ -1,3 +1,18 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64
|
||||
is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported.
|
||||
(targ_extra_emuls): Likewise.
|
||||
|
||||
* Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and
|
||||
eelf_l1om_fbsd.o
|
||||
(eelf_l1om.c): New.
|
||||
(eelf_l1om_fbsd.c): Likewise.
|
||||
* Makefile.in: Regenerated.
|
||||
|
||||
* emulparams/elf_l1om.sh: New.
|
||||
* emulparams/elf_l1om_fbsd.sh: Likewise.
|
||||
|
||||
2009-07-23 Ulrich Drepper <drepper@redhat.com>
|
||||
|
||||
* NEWS: Mention the linker's support for symbols with a binding of
|
||||
|
||||
@ -413,6 +413,8 @@ ALL_64_EMULATIONS = \
|
||||
eshlelf64_nbsd.o \
|
||||
eelf_x86_64.o \
|
||||
eelf_x86_64_fbsd.o \
|
||||
eelf_l1om.o \
|
||||
eelf_l1om_fbsd.o \
|
||||
eelf64_s390.o \
|
||||
eelf64_sparc.o \
|
||||
eelf64_sparc_fbsd.o \
|
||||
@ -1034,6 +1036,13 @@ eelf_x86_64_fbsd.c: $(srcdir)/emulparams/elf_x86_64_fbsd.sh \
|
||||
$(srcdir)/emulparams/elf_x86_64.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_x86_64_fbsd "$(tdir_elf_x86_64_fbsd)"
|
||||
eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)"
|
||||
eelf_l1om_fbsd.c: $(srcdir)/emulparams/elf_l1om_fbsd.sh \
|
||||
$(srcdir)/emulparams/elf_l1om.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_l1om_fbsd "$(tdir_elf_l1om_fbsd)"
|
||||
eelf_i386_be.c: $(srcdir)/emulparams/elf_i386_be.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_i386_be "$(tdir_elf_i386_be)"
|
||||
|
||||
@ -678,6 +678,8 @@ ALL_64_EMULATIONS = \
|
||||
eshlelf64_nbsd.o \
|
||||
eelf_x86_64.o \
|
||||
eelf_x86_64_fbsd.o \
|
||||
eelf_l1om.o \
|
||||
eelf_l1om_fbsd.o \
|
||||
eelf64_s390.o \
|
||||
eelf64_sparc.o \
|
||||
eelf64_sparc_fbsd.o \
|
||||
@ -1881,6 +1883,13 @@ eelf_x86_64_fbsd.c: $(srcdir)/emulparams/elf_x86_64_fbsd.sh \
|
||||
$(srcdir)/emulparams/elf_x86_64.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_x86_64_fbsd "$(tdir_elf_x86_64_fbsd)"
|
||||
eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)"
|
||||
eelf_l1om_fbsd.c: $(srcdir)/emulparams/elf_l1om_fbsd.sh \
|
||||
$(srcdir)/emulparams/elf_l1om.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_l1om_fbsd "$(tdir_elf_l1om_fbsd)"
|
||||
eelf_i386_be.c: $(srcdir)/emulparams/elf_i386_be.sh \
|
||||
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf_i386_be "$(tdir_elf_i386_be)"
|
||||
|
||||
@ -198,22 +198,22 @@ i[3-7]86-*-linux*aout*) targ_emul=i386linux
|
||||
i[3-7]86-*-linux*oldld) targ_emul=i386linux; targ_extra_emuls=elf_i386 ;;
|
||||
i[3-7]86-*-linux-*) targ_emul=elf_i386
|
||||
targ_extra_emuls=i386linux
|
||||
targ64_extra_emuls=elf_x86_64
|
||||
targ64_extra_emuls="elf_x86_64 elf_l1om"
|
||||
targ64_extra_libpath=elf_x86_64
|
||||
tdir_i386linux=${targ_alias}aout ;;
|
||||
x86_64-*-linux-*) targ_emul=elf_x86_64
|
||||
targ_extra_emuls="elf_i386 i386linux"
|
||||
targ_extra_emuls="elf_i386 i386linux elf_l1om"
|
||||
targ_extra_libpath=elf_i386
|
||||
tdir_i386linux=`echo ${targ_alias}aout | sed -e 's/x86_64/i386/'`
|
||||
tdir_elf_i386=`echo ${targ_alias} | sed -e 's/x86_64/i386/'` ;;
|
||||
i[3-7]86-*-sysv[45]*) targ_emul=elf_i386 ;;
|
||||
i[3-7]86-*-solaris2*) targ_emul=elf_i386_ldso
|
||||
targ_extra_emuls="elf_i386 elf_x86_64"
|
||||
targ_extra_emuls="elf_i386 elf_x86_64 elf_l1om"
|
||||
targ_extra_libpath=$targ_extra_emuls
|
||||
;;
|
||||
x86_64-*-solaris2*)
|
||||
targ_emul=elf_x86_64
|
||||
targ_extra_emuls="elf_i386 elf_i386_ldso"
|
||||
targ_extra_emuls="elf_i386 elf_i386_ldso elf_l1om"
|
||||
targ_extra_libpath=elf_i386
|
||||
tdir_elf_i386=`echo ${targ_alias} | sed -e 's/x86_64/i386/'` ;;
|
||||
i[3-7]86-*-unixware) targ_emul=elf_i386 ;;
|
||||
@ -231,7 +231,7 @@ i[3-7]86-*-netbsdpe*) targ_emul=i386pe
|
||||
i[3-7]86-*-netbsd*) targ_emul=i386nbsd
|
||||
targ_extra_emuls=elf_i386 ;;
|
||||
x86_64-*-netbsd*) targ_emul=elf_x86_64
|
||||
targ_extra_emuls="elf_i386 i386nbsd"
|
||||
targ_extra_emuls="elf_i386 i386nbsd elf_l1om"
|
||||
tdir_elf_i386=`echo ${targ_alias} | \
|
||||
sed -e 's/x86_64/i386/'`
|
||||
case "${tdir_elf_i386}" in
|
||||
@ -242,7 +242,7 @@ x86_64-*-netbsd*) targ_emul=elf_x86_64
|
||||
i[3-7]86-*-netware) targ_emul=i386nw ;;
|
||||
i[3-7]86-*-elf*) targ_emul=elf_i386 ;;
|
||||
x86_64-*-elf*) targ_emul=elf_x86_64
|
||||
targ_extra_emuls=elf_i386
|
||||
targ_extra_emuls="elf_i386 elf_l1om"
|
||||
;;
|
||||
i[3-7]86-*-kaos*) targ_emul=elf_i386 ;;
|
||||
i[3-7]86-*-freebsdaout* | i[3-7]86-*-freebsd[12].* | i[3-7]86-*-freebsd[12])
|
||||
@ -252,7 +252,7 @@ i[3-7]86-*-freebsd* | i[3-7]86-*-kfreebsd*-gnu | i[3-7]86-*-dragonfly*)
|
||||
targ_extra_emuls="elf_i386 i386bsd" ;;
|
||||
x86_64-*-freebsd* | x86_64-*-kfreebsd*-gnu)
|
||||
targ_emul=elf_x86_64_fbsd
|
||||
targ_extra_emuls="elf_i386_fbsd elf_x86_64 elf_i386"
|
||||
targ_extra_emuls="elf_i386_fbsd elf_x86_64 elf_i386 elf_l1om elf_l1om_fbsd"
|
||||
targ_extra_libpath="elf_i386_fbsd"
|
||||
tdir_elf_i386_fbsd=`echo ${targ_alias} \
|
||||
| sed -e 's/x86_64/i386/'`
|
||||
|
||||
@ -1,3 +1,12 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* ld-x86-64/abs-l1om.d: New.
|
||||
* ld-x86-64/protected2-l1om.d: Likewise.
|
||||
* ld-x86-64/protected3-l1om.d: Likewise.
|
||||
|
||||
* ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and
|
||||
protected3-l1om.
|
||||
|
||||
2009-07-24 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
|
||||
Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
|
||||
11
ld/testsuite/ld-x86-64/abs-l1om.d
Normal file
11
ld/testsuite/ld-x86-64/abs-l1om.d
Normal file
@ -0,0 +1,11 @@
|
||||
#name: Absolute non-overflowing relocs
|
||||
#source: ../ld-i386/abs.s
|
||||
#source: ../ld-i386/zero.s
|
||||
#as: --64 -march=l1om
|
||||
#ld: -m elf_l1om
|
||||
#objdump: -rs -j .text
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Contents of section \.text:
|
||||
[ ][0-9a-f]+ c800fff0 c8000110 c9c3.*
|
||||
17
ld/testsuite/ld-x86-64/protected2-l1om.d
Normal file
17
ld/testsuite/ld-x86-64/protected2-l1om.d
Normal file
@ -0,0 +1,17 @@
|
||||
#source: protected2.s
|
||||
#as: --64 -march=l1om
|
||||
#ld: -shared -melf_l1om
|
||||
#objdump: -drw --insn-width=7
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+[a-f0-9]+ <foo>:
|
||||
[ ]*[a-f0-9]+: c3 retq
|
||||
|
||||
0+[a-f0-9]+ <bar>:
|
||||
[ ]*[a-f0-9]+: e8 fa ff ff ff callq [a-f0-9]+ <foo>
|
||||
[ ]*[a-f0-9]+: c3 retq
|
||||
#pass
|
||||
16
ld/testsuite/ld-x86-64/protected3-l1om.d
Normal file
16
ld/testsuite/ld-x86-64/protected3-l1om.d
Normal file
@ -0,0 +1,16 @@
|
||||
#source: protected3.s
|
||||
#as: --64 -march=l1om
|
||||
#ld: -shared -melf_l1om
|
||||
#readelf: -h
|
||||
|
||||
ELF Header:
|
||||
Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00
|
||||
Class: ELF64
|
||||
Data: 2's complement, little endian
|
||||
Version: 1 \(current\)
|
||||
OS/ABI: UNIX - System V
|
||||
ABI Version: 0
|
||||
Type: DYN \(Shared object file\)
|
||||
Machine: Intel L1OM
|
||||
Version: 0x1
|
||||
#pass
|
||||
@ -80,6 +80,7 @@ set x86_64tests {
|
||||
run_ld_link_tests $x86_64tests
|
||||
|
||||
run_dump_test "abs"
|
||||
run_dump_test "abs-l1om"
|
||||
run_dump_test "pcrel8"
|
||||
run_dump_test "pcrel16"
|
||||
run_dump_test "tlsgd2"
|
||||
@ -91,5 +92,7 @@ run_dump_test "hidden2"
|
||||
run_dump_test "hidden3"
|
||||
run_dump_test "protected1"
|
||||
run_dump_test "protected2"
|
||||
run_dump_test "protected2-l1om"
|
||||
run_dump_test "protected3"
|
||||
run_dump_test "protected3-l1om"
|
||||
run_dump_test "tlsle1"
|
||||
|
||||
@ -1,3 +1,27 @@
|
||||
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* configure.in: Handle bfd_l1om_arch.
|
||||
* disassemble.c (disassembler): Likewise.
|
||||
|
||||
* configure: Regenerated.
|
||||
|
||||
* i386-dis.c (print_insn): Handle bfd_mach_l1om and
|
||||
bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM.
|
||||
|
||||
* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM.
|
||||
Add CPU_L1OM_FLAGS.
|
||||
(cpu_flags): Add CpuL1OM.
|
||||
(set_bitfield): Take an argument to set the value field.
|
||||
(process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY).
|
||||
(process_i386_opcode_modifier): Updated.
|
||||
(process_i386_operand_type): Likewise.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
* i386-opc.h (CpuL1OM): New.
|
||||
(CpuXsave): Updated.
|
||||
(i386_cpu_flags): Add cpul1om.
|
||||
|
||||
2009-07-24 Jan Beulich <jbeulich@novell.com>
|
||||
|
||||
* i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add
|
||||
|
||||
3
opcodes/configure
vendored
3
opcodes/configure
vendored
@ -12770,7 +12770,8 @@ if test x${all_targets} = xfalse ; then
|
||||
bfd_h8500_arch) ta="$ta h8500-dis.lo" ;;
|
||||
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
|
||||
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
|
||||
bfd_i386_arch) ta="$ta i386-dis.lo i386-opc.lo" ;;
|
||||
bfd_i386_arch|bfd_l1om_arch)
|
||||
ta="$ta i386-dis.lo i386-opc.lo" ;;
|
||||
bfd_i860_arch) ta="$ta i860-dis.lo" ;;
|
||||
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
||||
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
||||
|
||||
@ -221,7 +221,8 @@ if test x${all_targets} = xfalse ; then
|
||||
bfd_h8500_arch) ta="$ta h8500-dis.lo" ;;
|
||||
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
|
||||
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
|
||||
bfd_i386_arch) ta="$ta i386-dis.lo i386-opc.lo" ;;
|
||||
bfd_i386_arch|bfd_l1om_arch)
|
||||
ta="$ta i386-dis.lo i386-opc.lo" ;;
|
||||
bfd_i860_arch) ta="$ta i860-dis.lo" ;;
|
||||
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
||||
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
||||
|
||||
@ -197,6 +197,7 @@ disassembler (abfd)
|
||||
#endif
|
||||
#ifdef ARCH_i386
|
||||
case bfd_arch_i386:
|
||||
case bfd_arch_l1om:
|
||||
disassemble = print_insn_i386;
|
||||
break;
|
||||
#endif
|
||||
|
||||
@ -9415,19 +9415,24 @@ print_insn (bfd_vma pc, disassemble_info *info)
|
||||
char *prefix_obufp;
|
||||
|
||||
if (info->mach == bfd_mach_x86_64_intel_syntax
|
||||
|| info->mach == bfd_mach_x86_64)
|
||||
|| info->mach == bfd_mach_x86_64
|
||||
|| info->mach == bfd_mach_l1om
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax)
|
||||
address_mode = mode_64bit;
|
||||
else
|
||||
address_mode = mode_32bit;
|
||||
|
||||
if (intel_syntax == (char) -1)
|
||||
intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
|
||||
|| info->mach == bfd_mach_x86_64_intel_syntax);
|
||||
|| info->mach == bfd_mach_x86_64_intel_syntax
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax);
|
||||
|
||||
if (info->mach == bfd_mach_i386_i386
|
||||
|| info->mach == bfd_mach_x86_64
|
||||
|| info->mach == bfd_mach_l1om
|
||||
|| info->mach == bfd_mach_i386_i386_intel_syntax
|
||||
|| info->mach == bfd_mach_x86_64_intel_syntax)
|
||||
|| info->mach == bfd_mach_x86_64_intel_syntax
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax)
|
||||
priv.orig_sizeflag = AFLAG | DFLAG;
|
||||
else if (info->mach == bfd_mach_i386_i8086)
|
||||
priv.orig_sizeflag = 0;
|
||||
@ -9529,8 +9534,13 @@ print_insn (bfd_vma pc, disassemble_info *info)
|
||||
}
|
||||
|
||||
/* The output looks better if we put 7 bytes on a line, since that
|
||||
puts most long word instructions on a single line. */
|
||||
info->bytes_per_line = 7;
|
||||
puts most long word instructions on a single line. Use 8 bytes
|
||||
for Intel L1OM. */
|
||||
if (info->mach == bfd_mach_l1om
|
||||
|| info->mach == bfd_mach_l1om_intel_syntax)
|
||||
info->bytes_per_line = 8;
|
||||
else
|
||||
info->bytes_per_line = 7;
|
||||
|
||||
info->private_data = &priv;
|
||||
priv.max_fetched = priv.the_buffer;
|
||||
|
||||
@ -43,7 +43,7 @@ typedef struct initializer
|
||||
static initializer cpu_flag_init[] =
|
||||
{
|
||||
{ "CPU_UNKNOWN_FLAGS",
|
||||
"unknown" },
|
||||
"~CpuL1OM" },
|
||||
{ "CPU_GENERIC32_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386" },
|
||||
{ "CPU_GENERIC64_FLAGS",
|
||||
@ -150,6 +150,8 @@ static initializer cpu_flag_init[] =
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" },
|
||||
{ "CPU_ANY_AVX_FLAGS",
|
||||
"CpuAVX" },
|
||||
{ "CPU_L1OM_FLAGS",
|
||||
"unknown" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init[] =
|
||||
@ -280,6 +282,7 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (CpuSSE4_1),
|
||||
BITFIELD (CpuSSE4_2),
|
||||
BITFIELD (CpuAVX),
|
||||
BITFIELD (CpuL1OM),
|
||||
BITFIELD (CpuSSE4a),
|
||||
BITFIELD (Cpu3dnow),
|
||||
BITFIELD (Cpu3dnowA),
|
||||
@ -514,14 +517,15 @@ next_field (char *str, char sep, char **next, char *last)
|
||||
}
|
||||
|
||||
static void
|
||||
set_bitfield (const char *f, bitfield *array, unsigned int size, int lineno)
|
||||
set_bitfield (const char *f, bitfield *array, int value,
|
||||
unsigned int size, int lineno)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (strcmp (f, "CpuFP") == 0)
|
||||
{
|
||||
set_bitfield("Cpu387", array, size, lineno);
|
||||
set_bitfield("Cpu287", array, size, lineno);
|
||||
set_bitfield("Cpu387", array, value, size, lineno);
|
||||
set_bitfield("Cpu287", array, value, size, lineno);
|
||||
f = "Cpu8087";
|
||||
}
|
||||
else if (strcmp (f, "Mmword") == 0)
|
||||
@ -532,7 +536,7 @@ set_bitfield (const char *f, bitfield *array, unsigned int size, int lineno)
|
||||
for (i = 0; i < size; i++)
|
||||
if (strcasecmp (array[i].name, f) == 0)
|
||||
{
|
||||
array[i].value = 1;
|
||||
array[i].value = value;
|
||||
return;
|
||||
}
|
||||
|
||||
@ -572,6 +576,7 @@ process_i386_cpu_flag (FILE *table, char *flag, int macro,
|
||||
int lineno)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
unsigned int i;
|
||||
bitfield flags [ARRAY_SIZE (cpu_flags)];
|
||||
|
||||
/* Copy the default cpu flags. */
|
||||
@ -579,22 +584,50 @@ process_i386_cpu_flag (FILE *table, char *flag, int macro,
|
||||
|
||||
if (strcasecmp (flag, "unknown") == 0)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* We turn on everything except for cpu64 in case of
|
||||
CPU_UNKNOWN_FLAGS. */
|
||||
CPU_UNKNOWN_FLAGS. */
|
||||
for (i = 0; i < ARRAY_SIZE (flags); i++)
|
||||
if (flags[i].position != Cpu64)
|
||||
flags[i].value = 1;
|
||||
}
|
||||
else if (flag[0] == '~')
|
||||
{
|
||||
last = flag + strlen (flag);
|
||||
|
||||
if (flag[1] == '(')
|
||||
{
|
||||
last -= 1;
|
||||
next = flag + 2;
|
||||
if (*last != ')')
|
||||
fail (_("%s: %d: Missing `)' in bitfield: %s\n"), filename,
|
||||
lineno, flag);
|
||||
*last = '\0';
|
||||
}
|
||||
else
|
||||
next = flag + 1;
|
||||
|
||||
/* First we turn on everything except for cpu64. */
|
||||
for (i = 0; i < ARRAY_SIZE (flags); i++)
|
||||
if (flags[i].position != Cpu64)
|
||||
flags[i].value = 1;
|
||||
|
||||
/* Turn off selective bits. */
|
||||
for (; next && next < last; )
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, flags, 0, ARRAY_SIZE (flags), lineno);
|
||||
}
|
||||
}
|
||||
else if (strcmp (flag, "0"))
|
||||
{
|
||||
/* Turn on selective bits. */
|
||||
last = flag + strlen (flag);
|
||||
for (next = flag; next && next < last; )
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, flags, ARRAY_SIZE (flags), lineno);
|
||||
set_bitfield (str, flags, 1, ARRAY_SIZE (flags), lineno);
|
||||
}
|
||||
}
|
||||
|
||||
@ -635,7 +668,8 @@ process_i386_opcode_modifier (FILE *table, char *mod, int lineno)
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, modifiers, ARRAY_SIZE (modifiers), lineno);
|
||||
set_bitfield (str, modifiers, 1, ARRAY_SIZE (modifiers),
|
||||
lineno);
|
||||
}
|
||||
}
|
||||
output_opcode_modifier (table, modifiers, ARRAY_SIZE (modifiers));
|
||||
@ -682,7 +716,7 @@ process_i386_operand_type (FILE *table, char *op, int macro,
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, types, ARRAY_SIZE (types), lineno);
|
||||
set_bitfield (str, types, 1, ARRAY_SIZE (types), lineno);
|
||||
}
|
||||
}
|
||||
output_operand_type (table, types, ARRAY_SIZE (types), macro,
|
||||
|
||||
@ -21,273 +21,278 @@
|
||||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, \
|
||||
1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
||||
@ -88,8 +88,10 @@
|
||||
#define CpuSSE4_2 (CpuSSE4_1 + 1)
|
||||
/* AVX support required */
|
||||
#define CpuAVX (CpuSSE4_2 + 1)
|
||||
/* Intel L1OM support required */
|
||||
#define CpuL1OM (CpuAVX + 1)
|
||||
/* Xsave/xrstor New Instuctions support required */
|
||||
#define CpuXsave (CpuAVX + 1)
|
||||
#define CpuXsave (CpuL1OM + 1)
|
||||
/* AES support required */
|
||||
#define CpuAES (CpuXsave + 1)
|
||||
/* PCLMUL support required */
|
||||
@ -157,6 +159,7 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpusse4_1:1;
|
||||
unsigned int cpusse4_2:1;
|
||||
unsigned int cpuavx:1;
|
||||
unsigned int cpul1om:1;
|
||||
unsigned int cpuxsave:1;
|
||||
unsigned int cpuaes:1;
|
||||
unsigned int cpupclmul:1;
|
||||
|
||||
5400
opcodes/i386-tbl.h
5400
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user