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* mips-tdep.c (mips_insn32_frame_cache): Remove some dead code.
Minor reformatting. Some code factoring.
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@ -1,3 +1,8 @@
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2004-09-02 Joel Brobecker <brobecker@gnat.com>
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* mips-tdep.c (mips_insn32_frame_cache): Remove some dead code.
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Minor reformatting. Some code factoring.
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2004-09-02 Andrew Cagney <cagney@gnu.org>
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* config/vax/nbsd.mt (TM_FILE): Set to solib.h.
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@ -2118,28 +2118,16 @@ mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
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/* Bitmasks; set if we have found a save for the register. */
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unsigned long gen_save_found = 0;
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unsigned long float_save_found = 0;
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int mips16;
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/* If the address is odd, assume this is MIPS16 code. */
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addr = PROC_LOW_ADDR (proc_desc);
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mips16 = pc_is_mips16 (addr);
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/* Scan through this function's instructions preceding the
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current PC, and look for those that save registers. */
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while (addr < frame_pc_unwind (next_frame))
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{
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if (mips16)
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{
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mips16_decode_reg_save (mips16_fetch_instruction (addr),
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&gen_save_found);
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addr += MIPS16_INSTLEN;
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}
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else
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{
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mips32_decode_reg_save (mips32_fetch_instruction (addr),
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&gen_save_found, &float_save_found);
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addr += MIPS_INSTLEN;
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}
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mips32_decode_reg_save (mips32_fetch_instruction (addr),
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&gen_save_found, &float_save_found);
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addr += MIPS_INSTLEN;
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}
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gen_mask = gen_save_found;
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float_mask = float_save_found;
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@ -2159,48 +2147,20 @@ mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
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}
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}
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/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
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order of that normally used by gcc. Therefore, we have to fetch
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the first instruction of the function, and if it's an entry
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instruction that saves $s0 or $s1, correct their saved addresses. */
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if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
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{
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ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
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if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
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/* entry */
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{
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int reg;
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int sreg_count = (inst >> 6) & 3;
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/* Check if the ra register was pushed on the stack. */
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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if (inst & 0x20)
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reg_position -= mips_abi_regsize (gdbarch);
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/* Check if the s0 and s1 registers were pushed on the
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stack. */
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/* NOTE: cagney/2004-02-08: Huh? This is doing no such
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check. */
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for (reg = 16; reg < sreg_count + 16; reg++)
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{
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cache->saved_regs[NUM_REGS + reg].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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}
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}
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/* Fill in the offsets for the registers which float_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_FREG_OFFSET (proc_desc));
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CORE_ADDR reg_position = (cache->base + PROC_FREG_OFFSET (proc_desc));
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int ireg;
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/* Fill in the offsets for the float registers which float_mask
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says were saved. */
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for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
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if (float_mask & 0x80000000)
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{
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const int regno =
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NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg;
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if (mips_abi_regsize (gdbarch) == 4
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&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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{
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@ -2227,15 +2187,14 @@ mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
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reg_position is decremented each time through the
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loop). */
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if ((ireg & 1))
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position - mips_abi_regsize (gdbarch);
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cache->saved_regs[regno].addr =
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reg_position - mips_abi_regsize (gdbarch);
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position + mips_abi_regsize (gdbarch);
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cache->saved_regs[regno].addr =
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reg_position + mips_abi_regsize (gdbarch);
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}
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position;
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cache->saved_regs[regno].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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