Misc. changes I had lying around.

gdb/config/arc/arc.mt

@@ -1,8 +1,8 @@
 # Target: arc processor
-TDEPFILES= arc-tdep.o remote-arc.o 
-TM_FILE= tm-arc.h
+TDEPFILES = arc-tdep.o remote-arc.o
+TM_FILE = tm-arc.h
 
-REMOTE_OBS= dcache.o remote-utils.o
+REMOTE_OBS = dcache.o remote-utils.o # remote-sim.o
 
 # This isn't supported yet and prevents gdb from building.
 #SER_HARDWIRE= ser-go32-para.o

gdb/config/arc/tm-arc.h

@@ -53,14 +53,19 @@ extern CORE_ADDR skip_prologue PARAMS ((CORE_ADDR, int));
 #define BIG_BREAKPOINT { 0x12, 0x1f, 0xff, 0xff }
 #define LITTLE_BREAKPOINT { 0xff, 0xff, 0x1f, 0x12 }
 
-/* ??? This value may eventually be correct (if/when proper breakpoints
-   are added).  Until then no value is correct so leave as is and cope.  */
+/* Given the exposed pipeline, there isn't any one correct value.
+   However, this value must be 4.  GDB can't handle any other value (other than
+   zero).  See for example infrun.c:
+   "prev_pc != stop_pc - DECR_PC_AFTER_BREAK"  */
+/* FIXME */
 #define DECR_PC_AFTER_BREAK 8
 
 /* We don't have a reliable single step facility.
    ??? We do have a cycle single step facility, but that won't work.  */
 #define NO_SINGLE_STEP
 
+/* FIXME: Need to set STEP_SKIPS_DELAY.  */
+
 /* Given a pc value as defined by the hardware, return the real address.
    Remember that on the ARC blink contains that status register which
    includes PC + flags (so we have to mask out the flags).  */