mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-24 20:49:43 +00:00
gas/config/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Check suffix for crc32 in Intel mdoe. (process_suffix): Default the suffix of 8bit crc32 to BYTE_MNEM_SUFFIX. (check_byte_reg): Skip check for 8bit crc32. gas/testsuite/ 2007-05-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/crc32-intel.d: New file. * gas/i386/crc32.d:Likewise. * gas/i386/crc32.s:Likewise. * gas/i386/x86-64-crc32-intel.d:Likewise. * gas/i386/x86-64-crc32.d:Likewise. * gas/i386/x86-64-crc32.s:Likewise. * gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32 and x86-64-crc32-intel. opcodes/ 2007-05-01 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and check data size prefix in 16bit mode. * i386-opc.c (i386_optab): Default crc32 to non-8bit and support Intel mode.
This commit is contained in:
H.J. Lu
parent
3764ce598c
commit
9344ff2951
@ -1,3 +1,11 @@
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2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (match_template): Check suffix for crc32 in
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Intel mdoe.
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(process_suffix): Default the suffix of 8bit crc32 to
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BYTE_MNEM_SUFFIX.
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(check_byte_reg): Skip check for 8bit crc32.
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2007-04-30 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (md_assemble): Use register_prefix in
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@ -2557,9 +2557,11 @@ match_template (void)
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if (i.operands != t->operands)
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continue;
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/* Check the suffix, except for some instructions in intel mode. */
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/* Check the suffix, except for some instructions in intel mode.
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We do want to check suffix for crc32 even in intel mode. */
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if ((t->opcode_modifier & suffix_check)
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&& !(intel_syntax
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&& t->base_opcode != 0xf20f38f1
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&& (t->opcode_modifier & IgnoreSize)))
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continue;
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@ -2845,6 +2847,8 @@ process_suffix (void)
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i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
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LONG_MNEM_SUFFIX);
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}
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else if (i.tm.base_opcode == 0xf20f38f0)
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i.suffix = BYTE_MNEM_SUFFIX;
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if (!i.suffix)
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{
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@ -3040,6 +3044,10 @@ check_byte_reg (void)
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|| i.tm.base_opcode == 0xfbf))
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continue;
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/* crc32 doesn't generate this warning. */
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if (i.tm.base_opcode == 0xf20f38f0)
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continue;
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if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
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{
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/* Prohibit these changes in the 64bit mode, since the
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@ -1,3 +1,15 @@
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2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/crc32-intel.d: New file.
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* gas/i386/crc32.d:Likewise.
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* gas/i386/crc32.s:Likewise.
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* gas/i386/x86-64-crc32-intel.d:Likewise.
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* gas/i386/x86-64-crc32.d:Likewise.
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* gas/i386/x86-64-crc32.s:Likewise.
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* gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32
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and x86-64-crc32-intel.
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2007-04-26 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4430
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32
gas/testsuite/gas/i386/crc32-intel.d
Normal file
32
gas/testsuite/gas/i386/crc32-intel.d
Normal file
@ -0,0 +1,32 @@
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#objdump: -dwMintel
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#name: i386 crc32 (Intel disassembly)
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#source: crc32.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[esi\]
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[esi\]
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[esi\]
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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#pass
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31
gas/testsuite/gas/i386/crc32.d
Normal file
31
gas/testsuite/gas/i386/crc32.d
Normal file
@ -0,0 +1,31 @@
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#objdump: -dw
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#name: i386 crc32
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.*: file format .*
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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#pass
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31
gas/testsuite/gas/i386/crc32.s
Normal file
31
gas/testsuite/gas/i386/crc32.s
Normal file
@ -0,0 +1,31 @@
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# Check crc32 in SSE4.2
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.text
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foo:
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crc32b (%esi), %eax
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crc32w (%esi), %eax
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crc32l (%esi), %eax
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crc32 (%esi), %eax
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crc32 %al, %eax
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crc32b %al, %eax
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crc32 %ax, %eax
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crc32w %ax, %eax
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crc32 %eax, %eax
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crc32l %eax, %eax
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.intel_syntax noprefix
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crc32b eax,byte ptr [esi]
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crc32 eax,byte ptr [esi]
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crc32w eax, word ptr [esi]
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crc32 eax, word ptr [esi]
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crc32d eax,dword ptr [esi]
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crc32 eax,dword ptr [esi]
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crc32 eax,al
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crc32b eax,al
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crc32 eax, ax
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crc32w eax, ax
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crc32 eax,eax
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crc32d eax,eax
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.p2align 4,0
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@ -88,6 +88,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "addr32"
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run_dump_test "sse4_1"
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run_dump_test "sse4_2"
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run_dump_test "crc32"
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run_dump_test "crc32-intel"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -177,6 +179,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-nops-1-merom"
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run_dump_test "x86-64-sse4_1"
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run_dump_test "x86-64-sse4_2"
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run_dump_test "x86-64-crc32"
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run_dump_test "x86-64-crc32-intel"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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46
gas/testsuite/gas/i386/x86-64-crc32-intel.d
Normal file
46
gas/testsuite/gas/i386/x86-64-crc32-intel.d
Normal file
@ -0,0 +1,46 @@
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#objdump: -drwMintel
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#name: x86-64 crc32 (Intel mode)
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#source: x86-64-crc32.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b rax,BYTE PTR \[rsi\]
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q rax,QWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b rax,BYTE PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b rax,BYTE PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[rsi\]
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[rsi\]
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q rax,QWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q rax,QWORD PTR \[rsi\]
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax
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#pass
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45
gas/testsuite/gas/i386/x86-64-crc32.d
Normal file
45
gas/testsuite/gas/i386/x86-64-crc32.d
Normal file
@ -0,0 +1,45 @@
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#objdump: -dw
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#name: x86-64 crc32
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.*: file format .*
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax
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[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax
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#pass
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45
gas/testsuite/gas/i386/x86-64-crc32.s
Normal file
45
gas/testsuite/gas/i386/x86-64-crc32.s
Normal file
@ -0,0 +1,45 @@
|
||||
# crc32 in SSE4.2
|
||||
|
||||
.text
|
||||
foo:
|
||||
|
||||
crc32b (%rsi), %eax
|
||||
crc32b (%rsi), %rax
|
||||
crc32w (%rsi), %eax
|
||||
crc32l (%rsi), %eax
|
||||
crc32q (%rsi), %rax
|
||||
crc32 (%rsi), %eax
|
||||
crc32 %al, %eax
|
||||
crc32b %al, %eax
|
||||
crc32 %al, %rax
|
||||
crc32b %al, %rax
|
||||
crc32 %ax, %eax
|
||||
crc32w %ax, %eax
|
||||
crc32 %eax, %eax
|
||||
crc32l %eax, %eax
|
||||
crc32 %rax, %rax
|
||||
crc32q %rax, %rax
|
||||
|
||||
.intel_syntax noprefix
|
||||
crc32b rax,byte ptr [rsi]
|
||||
crc32 rax,byte ptr [rsi]
|
||||
crc32b eax,byte ptr [rsi]
|
||||
crc32 eax,byte ptr [rsi]
|
||||
crc32w eax, word ptr [rsi]
|
||||
crc32 eax, word ptr [rsi]
|
||||
crc32d eax,dword ptr [rsi]
|
||||
crc32 eax,dword ptr [rsi]
|
||||
crc32q rax,qword ptr [rsi]
|
||||
crc32 rax,qword ptr [rsi]
|
||||
crc32 eax,al
|
||||
crc32b eax,al
|
||||
crc32 rax,al
|
||||
crc32b rax,al
|
||||
crc32 eax, ax
|
||||
crc32w eax, ax
|
||||
crc32 eax,eax
|
||||
crc32d eax,eax
|
||||
crc32 rax,rax
|
||||
crc32q rax,rax
|
||||
|
||||
.p2align 4,0
|
||||
@ -1,3 +1,11 @@
|
||||
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
|
||||
check data size prefix in 16bit mode.
|
||||
|
||||
* i386-opc.c (i386_optab): Default crc32 to non-8bit and
|
||||
support Intel mode.
|
||||
|
||||
2007-04-30 Mark Salter <msalter@redhat.com>
|
||||
|
||||
* frv-desc.c: Regenerate.
|
||||
|
||||
@ -6390,13 +6390,11 @@ CRC32_Fixup (int bytemode, int sizeflag)
|
||||
USED_REX (REX_W);
|
||||
if (rex & REX_W)
|
||||
*p++ = 'q';
|
||||
else if ((prefixes & PREFIX_DATA))
|
||||
{
|
||||
*p++ = 'w';
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
else if (sizeflag & DFLAG)
|
||||
*p++ = intel_syntax ? 'd' : 'l';
|
||||
else
|
||||
*p++ = 'l';
|
||||
*p++ = 'w';
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
break;
|
||||
default:
|
||||
oappend (INTERNAL_DISASSEMBLER_ERROR);
|
||||
@ -6434,5 +6432,5 @@ CRC32_Fixup (int bytemode, int sizeflag)
|
||||
}
|
||||
}
|
||||
else
|
||||
OP_E (v_mode, sizeflag);
|
||||
OP_E (bytemode, sizeflag);
|
||||
}
|
||||
|
||||
@ -1442,10 +1442,12 @@ const template i386_optab[] =
|
||||
{"pcmpestrm", 3, 0x660f3a60,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
|
||||
{"pcmpistri", 3, 0x660f3a63,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
|
||||
{"pcmpistrm", 3, 0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
|
||||
{"crc32b", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8|ByteMem, Reg32|Reg64, 0 } },
|
||||
{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8, Reg32|Reg64, 0 } },
|
||||
/* We put non-8bit version before 8bit so that crc32 with memory operand
|
||||
defaults to non-8bit. */
|
||||
{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { WordReg|WordMem, Reg32, 0 } },
|
||||
{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } },
|
||||
{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, b_Suf|Modrm, { Reg8|ByteMem, Reg32, 0 } },
|
||||
{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|IgnoreSize|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } },
|
||||
|
||||
/* AMD 3DNow! instructions. */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user