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[AArch64] Fix +nofp16 handling
Feature flag handling was not perfect, +nofp16 disabled fp instructions too. New feature flag macros were added to check features with multiple bits set (matters for FP_F16 and SIMD_F16 opcode feature tests). The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE now checks all feature bits. The aarch64_features table now contains the dependencies as a separate field (so when the feature is enabled all dependencies are enabled and when it is disabled everything that depends on it is disabled). Note that armv8-a+foo+nofoo is not equivalent to armv8-a if +foo turns on dependent features that nofoo does not turn off. gas/ * config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add require field. (aarch64_features): Initialize require fields. (aarch64_parse_features): Handle dependencies. (aarch64_feature_enable_set, aarch64_feature_disable_set): New. (md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES. * testsuite/gas/aarch64/illegal-nofp16.s: New. * testsuite/gas/aarch64/illegal-nofp16.l: New. * testsuite/gas/aarch64/illegal-nofp16.d: New. include/ * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New. (AARCH64_CPU_HAS_ANY_FEATURES): New. (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES. (AARCH64_OPCODE_HAS_FEATURE): Remove.
This commit is contained in:
Szabolcs Nagy
parent
2c5c2a3321
commit
93d8990cba
@ -1,3 +1,15 @@
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2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
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require field.
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(aarch64_features): Initialize require fields.
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(aarch64_parse_features): Handle dependencies.
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(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
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(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
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* testsuite/gas/aarch64/illegal-nofp16.s: New.
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* testsuite/gas/aarch64/illegal-nofp16.l: New.
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* testsuite/gas/aarch64/illegal-nofp16.d: New.
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2016-07-01 Nick Clifton <nickc@redhat.com>
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* macro.c (macro_expand_body): Use a buffer big enough to hold an
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@ -6080,7 +6080,7 @@ md_assemble (char *str)
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{
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/* Check that this instruction is supported for this CPU. */
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if (!opcode->avariant
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|| !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
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|| !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
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{
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as_bad (_("selected processor does not support `%s'"), str);
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return;
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@ -7801,23 +7801,33 @@ struct aarch64_option_cpu_value_table
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{
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const char *name;
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const aarch64_feature_set value;
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const aarch64_feature_set require; /* Feature dependencies. */
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};
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static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
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{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
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{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
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{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
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{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
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{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
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{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
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{"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0)},
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{"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
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| AARCH64_FEATURE_RDMA, 0)},
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{"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
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| AARCH64_FEATURE_FP, 0)},
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{"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0)},
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{NULL, AARCH64_ARCH_NONE}
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{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
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AARCH64_ARCH_NONE},
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{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
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AARCH64_ARCH_NONE},
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{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
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AARCH64_ARCH_NONE},
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{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
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AARCH64_ARCH_NONE},
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{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
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AARCH64_ARCH_NONE},
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{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
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AARCH64_ARCH_NONE},
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{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
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AARCH64_ARCH_NONE},
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{"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0),
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AARCH64_ARCH_NONE},
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{"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
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{"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
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{"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
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AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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struct aarch64_long_option_table
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@ -7828,6 +7838,38 @@ struct aarch64_long_option_table
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char *deprecated; /* If non-null, print this message. */
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};
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/* Transitive closure of features depending on set. */
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static aarch64_feature_set
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aarch64_feature_disable_set (aarch64_feature_set set)
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{
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const struct aarch64_option_cpu_value_table *opt;
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aarch64_feature_set prev = 0;
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while (prev != set) {
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prev = set;
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for (opt = aarch64_features; opt->name != NULL; opt++)
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if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set))
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AARCH64_MERGE_FEATURE_SETS (set, set, opt->value);
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}
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return set;
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}
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/* Transitive closure of dependencies of set. */
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static aarch64_feature_set
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aarch64_feature_enable_set (aarch64_feature_set set)
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{
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const struct aarch64_option_cpu_value_table *opt;
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aarch64_feature_set prev = 0;
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while (prev != set) {
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prev = set;
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for (opt = aarch64_features; opt->name != NULL; opt++)
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if (AARCH64_CPU_HAS_FEATURE (set, opt->value))
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AARCH64_MERGE_FEATURE_SETS (set, set, opt->require);
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}
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return set;
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}
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static int
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aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
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bfd_boolean ext_only)
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@ -7895,11 +7937,19 @@ aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
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for (opt = aarch64_features; opt->name != NULL; opt++)
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if (strncmp (opt->name, str, optlen) == 0)
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{
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aarch64_feature_set set;
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/* Add or remove the extension. */
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if (adding_value)
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AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
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{
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set = aarch64_feature_enable_set (opt->value);
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AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set);
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}
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else
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AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
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{
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set = aarch64_feature_disable_set (opt->value);
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AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set);
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}
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break;
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}
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2
gas/testsuite/gas/aarch64/illegal-nofp16.d
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2
gas/testsuite/gas/aarch64/illegal-nofp16.d
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@ -0,0 +1,2 @@
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#as: -march=armv8.2-a+nofp16 -mno-verbose-error
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#error-output: illegal-nofp16.l
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3
gas/testsuite/gas/aarch64/illegal-nofp16.l
Normal file
3
gas/testsuite/gas/aarch64/illegal-nofp16.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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^[^:]+:4: Error: selected processor does not support `fneg h0,h1'
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^[^:]+:6: Error: selected processor does not support `fneg v0\.8h,v1\.8h'
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7
gas/testsuite/gas/aarch64/illegal-nofp16.s
Normal file
7
gas/testsuite/gas/aarch64/illegal-nofp16.s
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@ -0,0 +1,7 @@
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// Test -march=armv8.2-a+nofp16 to only disable fp16, not fp.
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.text
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fneg s0, s1
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fneg h0, h1
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fneg v0.4s, v1.4s
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fneg v0.8h, v1.8h
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neg v0.16b, v1.16b
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@ -1,3 +1,10 @@
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2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
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(AARCH64_CPU_HAS_ANY_FEATURES): New.
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(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
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(AARCH64_OPCODE_HAS_FEATURE): Remove.
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2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
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* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
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@ -84,9 +84,15 @@ typedef uint32_t aarch64_insn;
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/* CPU-specific features. */
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typedef unsigned long aarch64_feature_set;
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#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
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#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
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((~(CPU) & (FEAT)) == 0)
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#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
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(((CPU) & (FEAT)) != 0)
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#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
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AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
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#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
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do \
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{ \
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@ -103,9 +109,6 @@ typedef unsigned long aarch64_feature_set;
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#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
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#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
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(((OPC) & (FEAT)) != 0)
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enum aarch64_operand_class
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{
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AARCH64_OPND_CLASS_NIL,
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