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https://github.com/darlinghq/darling-gdb.git
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[ gas/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
(mips_immed): New table that records various handling of udi
instruction patterns.
(mips_ip): Adds udi handling.
[ include/opcode/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
instructions.
[ opcodes/ChangeLog ]
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips-opc.c (mips_builtin_opcodes): Add udi instructions
"udi0" to "udi15".
* mips-dis.c (print_insn_args): Adds udi argument handling.
This commit is contained in:
Thiemo Seufer
parent
da54898db3
commit
9bcd4f993c
@ -1,3 +1,11 @@
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2006-04-30 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
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(mips_immed): New table that records various handling of udi
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instruction patterns.
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(mips_ip): Adds udi handling.
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2006-04-28 Alan Modra <amodra@bigpond.net.au>
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* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
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@ -7814,6 +7814,10 @@ validate_mips_insn (const struct mips_opcode *opc)
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case '+':
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switch (c = *p++)
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{
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case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
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case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
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case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
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case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
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case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
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case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
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case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
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@ -7919,6 +7923,22 @@ validate_mips_insn (const struct mips_opcode *opc)
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return 1;
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}
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/* UDI immediates. */
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struct mips_immed {
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char type;
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unsigned int shift;
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unsigned long mask;
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const char * desc;
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};
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static const struct mips_immed mips_immed[] = {
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{ '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
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{ '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
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{ '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
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{ '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
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{ 0,0,0,0 }
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};
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/* This routine assembles an instruction into its binary format. As a
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side effect, it sets one of the global variables imm_reloc or
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offset_reloc to the type of relocation to do if one of the operands
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@ -8324,6 +8344,34 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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case '+': /* Opcode extension character. */
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switch (*++args)
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{
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case '1': /* UDI immediates. */
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case '2':
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case '3':
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case '4':
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{
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const struct mips_immed *imm = mips_immed;
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while (imm->type && imm->type != *args)
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++imm;
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if (! imm->type)
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internalError ();
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
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{
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as_warn (_("Illegal %s number (%lu, 0x%lx)"),
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imm->desc ? imm->desc : ip->insn_mo->name,
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(unsigned long) imm_expr.X_add_number,
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(unsigned long) imm_expr.X_add_number);
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imm_expr.X_add_number &= imm->mask;
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}
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ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
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<< imm->shift);
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imm_expr.X_op = O_absent;
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s = expr_end;
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}
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continue;
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case 'A': /* ins/ext position, becomes LSB. */
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limlo = 0;
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limhi = 31;
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@ -1,3 +1,10 @@
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2006-04-30 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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* mips.h: Defines udi bits and masks. Add description of
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characters which may appear in the args field of udi
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instructions.
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2006-04-26 Thiemo Seufer <ths@networkno.de>
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* mips.h: Improve comments describing the bitfield instruction
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@ -203,6 +203,16 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
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#define MDMX_FMTSEL_VEC_QH 0x15
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#define MDMX_FMTSEL_VEC_OB 0x16
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/* UDI */
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#define OP_SH_UDI1 6
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#define OP_MASK_UDI1 0x1f
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#define OP_SH_UDI2 6
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#define OP_MASK_UDI2 0x3ff
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#define OP_SH_UDI3 6
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#define OP_MASK_UDI3 0x7fff
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#define OP_SH_UDI4 6
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#define OP_MASK_UDI4 0xfffff
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/* This structure holds information for a particular instruction. */
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struct mips_opcode
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@ -351,6 +361,12 @@ struct mips_opcode
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"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
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"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
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UDI immediates:
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"+1" UDI immediate bits 6-10
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"+2" UDI immediate bits 6-15
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"+3" UDI immediate bits 6-20
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"+4" UDI immediate bits 6-25
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Other:
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"()" parens surrounding optional value
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"," separates operands
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@ -365,6 +381,7 @@ struct mips_opcode
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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"1234"
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"ABCDEFGHIT"
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"t"
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*/
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@ -1,3 +1,10 @@
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2006-04-30 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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* mips-opc.c (mips_builtin_opcodes): Add udi instructions
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"udi0" to "udi15".
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* mips-dis.c (print_insn_args): Adds udi argument handling.
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2006-04-28 James E Wilson <wilson@specifix.com>
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* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
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@ -753,6 +753,26 @@ print_insn_args (const char *d,
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(*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
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break;
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case '1':
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_UDI1) & OP_MASK_UDI1);
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break;
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case '2':
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_UDI2) & OP_MASK_UDI2);
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break;
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case '3':
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_UDI3) & OP_MASK_UDI3);
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break;
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case '4':
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(*info->fprintf_func) (info->stream, "0x%lx",
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(l >> OP_SH_UDI4) & OP_MASK_UDI4);
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break;
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case 'C':
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case 'H':
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msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
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@ -1263,6 +1263,72 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
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{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
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/* User Defined Instruction. */
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{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
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instructions so they are here for the latters to take precedence. */
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{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
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