mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-02-10 11:12:23 +00:00
* gas/config/tc-arm.c (do_rm_rn): New function.
(do_strlex): Likewise. (do_t_strlex): Likewise. (insns): Add support for LDRA/STRL instructions. * gas/testsuite/gas/arm/armv8-a-bad.l: Update testcase. * gas/testsuite/gas/arm/armv8-a-bad.s: Likewise. * gas/testsuite/gas/arm/armv8-a.d: Likewise. * gas/testsuite/gas/arm/armv8-a.s: Likewise. * opcodes/arm-dis.c (arm_opcodes): Add LDRA/STRL instructions. (thumb32_opcodes): Likewise. (print_arm_insn): Add support for %<>T formatter.
This commit is contained in:
Matthew Gretton-Dann
parent
8884b7208b
commit
9eb6c0f132
@ -1,3 +1,10 @@
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* config/tc-arm.c (do_rm_rn): New function.
|
||||
(do_strlex): Likewise.
|
||||
(do_t_strlex): Likewise.
|
||||
(insns): Add support for LDRA/STRL instructions.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* config/tc-arm.c (do_t_bkpt_hlt1): New function.
|
||||
|
||||
@ -7382,6 +7382,13 @@ do_rd_rm (void)
|
||||
inst.instruction |= inst.operands[1].reg;
|
||||
}
|
||||
|
||||
static void
|
||||
do_rm_rn (void)
|
||||
{
|
||||
inst.instruction |= inst.operands[0].reg;
|
||||
inst.instruction |= inst.operands[1].reg << 16;
|
||||
}
|
||||
|
||||
static void
|
||||
do_rd_rn (void)
|
||||
{
|
||||
@ -8729,6 +8736,25 @@ do_strexd (void)
|
||||
inst.instruction |= inst.operands[3].reg << 16;
|
||||
}
|
||||
|
||||
/* ARM V8 STRL. */
|
||||
static void
|
||||
do_strlex (void)
|
||||
{
|
||||
constraint (inst.operands[0].reg == inst.operands[1].reg
|
||||
|| inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
|
||||
|
||||
do_rd_rm_rn ();
|
||||
}
|
||||
|
||||
static void
|
||||
do_t_strlex (void)
|
||||
{
|
||||
constraint (inst.operands[0].reg == inst.operands[1].reg
|
||||
|| inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
|
||||
|
||||
do_rm_rd_rn ();
|
||||
}
|
||||
|
||||
/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
|
||||
extends it to 32-bits, and adds the result to a value in another
|
||||
register. You can specify a rotation by 0, 8, 16, or 24 bits
|
||||
@ -17991,6 +18017,25 @@ static const struct asm_opcode insns[] =
|
||||
|
||||
tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
|
||||
TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
|
||||
TCE("ldraex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
|
||||
TCE("ldraexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
|
||||
ldrexd, t_ldrexd),
|
||||
TCE("ldraexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
|
||||
TCE("ldraexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
|
||||
TCE("strlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
|
||||
strlex, t_strlex),
|
||||
TCE("strlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
|
||||
strexd, t_strexd),
|
||||
TCE("strlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
|
||||
strlex, t_strlex),
|
||||
TCE("strlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
|
||||
strlex, t_strlex),
|
||||
TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
|
||||
TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
|
||||
TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
|
||||
TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
|
||||
TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
|
||||
TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
|
||||
|
||||
/* ARMv8 T32 only. */
|
||||
#undef ARM_VARIANT
|
||||
|
||||
@ -1,3 +1,10 @@
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* gas/arm/armv8-a-bad.l: Update testcase.
|
||||
* gas/arm/armv8-a-bad.s: Likewise.
|
||||
* gas/arm/armv8-a.d: Likewise.
|
||||
* gas/arm/armv8-a.s: Likewise.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* gas/arm/armv8-a-bad.l: Update for HLT.
|
||||
|
||||
@ -12,3 +12,85 @@
|
||||
.*:29: Error: immediate value out of range -- `hlt 64'
|
||||
.*:31: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
|
||||
.*:31: Error: instruction is always unconditional -- `hltne 0'
|
||||
.*:35: Error: r15 not allowed here -- `strlb pc,\[r0\]'
|
||||
.*:36: Error: r15 not allowed here -- `strlb r0,\[pc\]'
|
||||
.*:37: Error: r15 not allowed here -- `strlh pc,\[r0\]'
|
||||
.*:38: Error: r15 not allowed here -- `strlh r0,\[pc\]'
|
||||
.*:39: Error: r15 not allowed here -- `strl pc,\[r0\]'
|
||||
.*:40: Error: r15 not allowed here -- `strl r0,\[pc\]'
|
||||
.*:41: Error: r15 not allowed here -- `strlexb r1,pc,\[r0\]'
|
||||
.*:42: Error: r15 not allowed here -- `strlexb r1,r0,\[pc\]'
|
||||
.*:43: Error: r15 not allowed here -- `strlexb pc,r0,\[r1\]'
|
||||
.*:44: Error: registers may not be the same -- `strlexb r0,r0,\[r1\]'
|
||||
.*:45: Error: registers may not be the same -- `strlexb r0,r1,\[r0\]'
|
||||
.*:46: Error: r15 not allowed here -- `strlexh r1,pc,\[r0\]'
|
||||
.*:47: Error: r15 not allowed here -- `strlexh r1,r0,\[pc\]'
|
||||
.*:48: Error: r15 not allowed here -- `strlexh pc,r0,\[r1\]'
|
||||
.*:49: Error: registers may not be the same -- `strlexh r0,r0,\[r1\]'
|
||||
.*:50: Error: registers may not be the same -- `strlexh r0,r1,\[r0\]'
|
||||
.*:51: Error: r15 not allowed here -- `strlex r1,pc,\[r0\]'
|
||||
.*:52: Error: r15 not allowed here -- `strlex r1,r0,\[pc\]'
|
||||
.*:53: Error: r15 not allowed here -- `strlex pc,r0,\[r1\]'
|
||||
.*:54: Error: registers may not be the same -- `strlex r0,r0,\[r1\]'
|
||||
.*:55: Error: registers may not be the same -- `strlex r0,r1,\[r0\]'
|
||||
.*:56: Error: r14 not allowed here -- `strlexd r1,lr,\[r0\]'
|
||||
.*:57: Error: r15 not allowed here -- `strlexd r1,r0,\[pc\]'
|
||||
.*:58: Error: r15 not allowed here -- `strlexd pc,r0,\[r1\]'
|
||||
.*:59: Error: registers may not be the same -- `strlexd r0,r0,\[r1\]'
|
||||
.*:60: Error: registers may not be the same -- `strlexd r0,r2,\[r0\]'
|
||||
.*:61: Error: even register required -- `strlexd r0,r1,\[r2\]'
|
||||
.*:65: Error: r15 not allowed here -- `strlb pc,\[r0\]'
|
||||
.*:66: Error: r15 not allowed here -- `strlb r0,\[pc\]'
|
||||
.*:67: Error: r15 not allowed here -- `strlh pc,\[r0\]'
|
||||
.*:68: Error: r15 not allowed here -- `strlh r0,\[pc\]'
|
||||
.*:69: Error: r15 not allowed here -- `strl pc,\[r0\]'
|
||||
.*:70: Error: r15 not allowed here -- `strl r0,\[pc\]'
|
||||
.*:71: Error: r15 not allowed here -- `strlexb r1,pc,\[r0\]'
|
||||
.*:72: Error: r15 not allowed here -- `strlexb r1,r0,\[pc\]'
|
||||
.*:73: Error: r15 not allowed here -- `strlexb pc,r0,\[r1\]'
|
||||
.*:74: Error: registers may not be the same -- `strlexb r0,r0,\[r1\]'
|
||||
.*:75: Error: registers may not be the same -- `strlexb r0,r1,\[r0\]'
|
||||
.*:76: Error: r15 not allowed here -- `strlexh r1,pc,\[r0\]'
|
||||
.*:77: Error: r15 not allowed here -- `strlexh r1,r0,\[pc\]'
|
||||
.*:78: Error: r15 not allowed here -- `strlexh pc,r0,\[r1\]'
|
||||
.*:79: Error: registers may not be the same -- `strlexh r0,r0,\[r1\]'
|
||||
.*:80: Error: registers may not be the same -- `strlexh r0,r1,\[r0\]'
|
||||
.*:81: Error: r15 not allowed here -- `strlex r1,pc,\[r0\]'
|
||||
.*:82: Error: r15 not allowed here -- `strlex r1,r0,\[pc\]'
|
||||
.*:83: Error: r15 not allowed here -- `strlex pc,r0,\[r1\]'
|
||||
.*:84: Error: registers may not be the same -- `strlex r0,r0,\[r1\]'
|
||||
.*:85: Error: registers may not be the same -- `strlex r0,r1,\[r0\]'
|
||||
.*:87: Error: r15 not allowed here -- `strlexd r1,r0,\[pc\]'
|
||||
.*:88: Error: r15 not allowed here -- `strlexd pc,r0,\[r1\]'
|
||||
.*:89: Error: registers may not be the same -- `strlexd r0,r0,\[r1\]'
|
||||
.*:90: Error: registers may not be the same -- `strlexd r0,r2,\[r0\]'
|
||||
.*:95: Error: r15 not allowed here -- `ldrab pc,\[r0\]'
|
||||
.*:96: Error: r15 not allowed here -- `ldrab r0,\[pc\]'
|
||||
.*:97: Error: r15 not allowed here -- `ldrah pc,\[r0\]'
|
||||
.*:98: Error: r15 not allowed here -- `ldrah r0,\[pc\]'
|
||||
.*:99: Error: r15 not allowed here -- `ldra pc,\[r0\]'
|
||||
.*:100: Error: r15 not allowed here -- `ldra r0,\[pc\]'
|
||||
.*:101: Error: r15 not allowed here -- `ldraexb pc,\[r0\]'
|
||||
.*:102: Error: r15 not allowed here -- `ldraexb r0,\[pc\]'
|
||||
.*:103: Error: r15 not allowed here -- `ldraexh pc,\[r0\]'
|
||||
.*:104: Error: r15 not allowed here -- `ldraexh r0,\[pc\]'
|
||||
.*:105: Error: r15 not allowed here -- `ldraex pc,\[r0\]'
|
||||
.*:106: Error: r15 not allowed here -- `ldraex r0,\[pc\]'
|
||||
.*:107: Error: r14 not allowed here -- `ldraexd lr,\[r0\]'
|
||||
.*:108: Error: r15 not allowed here -- `ldraexd r0,\[pc\]'
|
||||
.*:109: Error: even register required -- `ldraexd r1,\[r2\]'
|
||||
.*:113: Error: r15 not allowed here -- `ldrab pc,\[r0\]'
|
||||
.*:114: Error: r15 not allowed here -- `ldrab r0,\[pc\]'
|
||||
.*:115: Error: r15 not allowed here -- `ldrah pc,\[r0\]'
|
||||
.*:116: Error: r15 not allowed here -- `ldrah r0,\[pc\]'
|
||||
.*:117: Error: r15 not allowed here -- `ldra pc,\[r0\]'
|
||||
.*:118: Error: r15 not allowed here -- `ldra r0,\[pc\]'
|
||||
.*:119: Error: r15 not allowed here -- `ldraexb pc,\[r0\]'
|
||||
.*:120: Error: r15 not allowed here -- `ldraexb r0,\[pc\]'
|
||||
.*:121: Error: r15 not allowed here -- `ldraexh pc,\[r0\]'
|
||||
.*:122: Error: r15 not allowed here -- `ldraexh r0,\[pc\]'
|
||||
.*:123: Error: r15 not allowed here -- `ldraex pc,\[r0\]'
|
||||
.*:124: Error: r15 not allowed here -- `ldraex r0,\[pc\]'
|
||||
.*:125: Error: r15 not allowed here -- `ldraexd r0,pc,\[r0\]'
|
||||
.*:126: Error: r15 not allowed here -- `ldraexd pc,r0,\[r0\]'
|
||||
.*:127: Error: r15 not allowed here -- `ldraexd r1,r0,\[pc\]'
|
||||
|
||||
@ -29,3 +29,99 @@
|
||||
hlt 64
|
||||
it ne
|
||||
hltne 0
|
||||
|
||||
// STRL A32
|
||||
.arm
|
||||
strlb pc, [r0]
|
||||
strlb r0, [pc]
|
||||
strlh pc, [r0]
|
||||
strlh r0, [pc]
|
||||
strl pc, [r0]
|
||||
strl r0, [pc]
|
||||
strlexb r1, pc, [r0]
|
||||
strlexb r1, r0, [pc]
|
||||
strlexb pc, r0, [r1]
|
||||
strlexb r0, r0, [r1]
|
||||
strlexb r0, r1, [r0]
|
||||
strlexh r1, pc, [r0]
|
||||
strlexh r1, r0, [pc]
|
||||
strlexh pc, r0, [r1]
|
||||
strlexh r0, r0, [r1]
|
||||
strlexh r0, r1, [r0]
|
||||
strlex r1, pc, [r0]
|
||||
strlex r1, r0, [pc]
|
||||
strlex pc, r0, [r1]
|
||||
strlex r0, r0, [r1]
|
||||
strlex r0, r1, [r0]
|
||||
strlexd r1, lr, [r0]
|
||||
strlexd r1, r0, [pc]
|
||||
strlexd pc, r0, [r1]
|
||||
strlexd r0, r0, [r1]
|
||||
strlexd r0, r2, [r0]
|
||||
strlexd r0, r1, [r2]
|
||||
|
||||
// STRL T32
|
||||
.thumb
|
||||
strlb pc, [r0]
|
||||
strlb r0, [pc]
|
||||
strlh pc, [r0]
|
||||
strlh r0, [pc]
|
||||
strl pc, [r0]
|
||||
strl r0, [pc]
|
||||
strlexb r1, pc, [r0]
|
||||
strlexb r1, r0, [pc]
|
||||
strlexb pc, r0, [r1]
|
||||
strlexb r0, r0, [r1]
|
||||
strlexb r0, r1, [r0]
|
||||
strlexh r1, pc, [r0]
|
||||
strlexh r1, r0, [pc]
|
||||
strlexh pc, r0, [r1]
|
||||
strlexh r0, r0, [r1]
|
||||
strlexh r0, r1, [r0]
|
||||
strlex r1, pc, [r0]
|
||||
strlex r1, r0, [pc]
|
||||
strlex pc, r0, [r1]
|
||||
strlex r0, r0, [r1]
|
||||
strlex r0, r1, [r0]
|
||||
strlexd r1, lr, [r0]
|
||||
strlexd r1, r0, [pc]
|
||||
strlexd pc, r0, [r1]
|
||||
strlexd r0, r0, [r1]
|
||||
strlexd r0, r2, [r0]
|
||||
strlexd r0, r1, [r2]
|
||||
|
||||
// LDRA A32
|
||||
.arm
|
||||
ldrab pc, [r0]
|
||||
ldrab r0, [pc]
|
||||
ldrah pc, [r0]
|
||||
ldrah r0, [pc]
|
||||
ldra pc, [r0]
|
||||
ldra r0, [pc]
|
||||
ldraexb pc, [r0]
|
||||
ldraexb r0, [pc]
|
||||
ldraexh pc, [r0]
|
||||
ldraexh r0, [pc]
|
||||
ldraex pc, [r0]
|
||||
ldraex r0, [pc]
|
||||
ldraexd lr, [r0]
|
||||
ldraexd r0, [pc]
|
||||
ldraexd r1, [r2]
|
||||
|
||||
// LDRA T32
|
||||
.thumb
|
||||
ldrab pc, [r0]
|
||||
ldrab r0, [pc]
|
||||
ldrah pc, [r0]
|
||||
ldrah r0, [pc]
|
||||
ldra pc, [r0]
|
||||
ldra r0, [pc]
|
||||
ldraexb pc, [r0]
|
||||
ldraexb r0, [pc]
|
||||
ldraexh pc, [r0]
|
||||
ldraexh r0, [pc]
|
||||
ldraex pc, [r0]
|
||||
ldraex r0, [pc]
|
||||
ldraexd r0, pc, [r0]
|
||||
ldraexd pc, r0, [r0]
|
||||
ldraexd r1, r0, [pc]
|
||||
|
||||
@ -8,6 +8,48 @@ Disassembly of section .text:
|
||||
0[0-9a-f]+ <[^>]+> e1000070 hlt 0x0000
|
||||
0[0-9a-f]+ <[^>]+> e100007f hlt 0x000f
|
||||
0[0-9a-f]+ <[^>]+> e10fff70 hlt 0xfff0
|
||||
0[0-9a-f]+ <[^>]+> e1c0fc90 strlb r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1c1fc91 strlb r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1cefc9e strlb lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1e0fc90 strlh r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1e1fc91 strlh r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1eefc9e strlh lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e180fc90 strl r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e181fc91 strl r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e18efc9e strl lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1ce0e91 strlexb r0, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1c01e9e strlexb r1, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1c1ee90 strlexb lr, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1ee0e91 strlexh r0, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1e01e9e strlexh r1, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1e1ee90 strlexh lr, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e18e0e91 strlex r0, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1801e9e strlex r1, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e181ee90 strlex lr, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1ae0e92 strlexd r0, r2, r3, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1a01e9c strlexd r1, ip, sp, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1a1ee90 strlexd lr, r0, r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1d00c9f ldrab r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1d11c9f ldrab r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1deec9f ldrab lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1f00c9f ldraexh r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1f11c9f ldraexh r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1feec9f ldraexh lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1900c9f ldra r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1911c9f ldra r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e19eec9f ldra lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1d00e9f ldraexb r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1d11e9f ldraexb r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1deee9f ldraexb lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1f00e9f ldraexh r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1f11e9f ldraexh r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1feee9f ldraexh lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1900e9f ldraex r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1911e9f ldraex r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e19eee9f ldraex lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e1b00e9f ldraexd r0, r1, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e1b12e9f ldraexd r2, r3, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e1bece9f ldraexd ip, sp, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> bf50 sevl
|
||||
0[0-9a-f]+ <[^>]+> bf50 sevl
|
||||
0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
|
||||
@ -16,3 +58,45 @@ Disassembly of section .text:
|
||||
0[0-9a-f]+ <[^>]+> f78f 8003 dcps3
|
||||
0[0-9a-f]+ <[^>]+> ba80 hlt 0x0000
|
||||
0[0-9a-f]+ <[^>]+> babf hlt 0x003f
|
||||
0[0-9a-f]+ <[^>]+> e8c0 0f8f strlb r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 1f8f strlb r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce ef8f strlb lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8c0 0f9f strlh r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 1f9f strlh r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce ef9f strlh lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8c0 0faf strl r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 1faf strl r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce efaf strl lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce 1fc0 strlexb r0, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8c0 efc1 strlexb r1, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 0fce strlexb lr, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce 1fd0 strlexh r0, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8c0 efd1 strlexh r1, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 0fde strlexh lr, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce 1fe0 strlex r0, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8c0 efe1 strlex r1, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 0fee strlex lr, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8ce 11f0 strlexd r0, r1, r1, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8c0 eef1 strlexd r1, lr, lr, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8c1 00fe strlexd lr, r0, r0, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 0f8f ldrab r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1f8f ldrab r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de ef8f ldrab lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 0f9f ldrah r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1f9f ldrah r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de ef9f ldrah lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 0faf ldra r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1faf ldra r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de efaf ldra lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 0fcf ldraexb r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1fcf ldraexb r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de efcf ldraexb lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 0fdf ldraexh r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1fdf ldraexh r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de efdf ldraexh lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 0fef ldraex r0, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1fef ldraex r1, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de efef ldraex lr, \[lr\]
|
||||
0[0-9a-f]+ <[^>]+> e8d0 01ff ldraexd r0, r1, \[r0\]
|
||||
0[0-9a-f]+ <[^>]+> e8d1 1eff ldraexd r1, lr, \[r1\]
|
||||
0[0-9a-f]+ <[^>]+> e8de e0ff ldraexd lr, r0, \[lr\]
|
||||
|
||||
@ -8,6 +8,48 @@ foo:
|
||||
hlt 0x0
|
||||
hlt 0xf
|
||||
hlt 0xfff0
|
||||
strlb r0, [r0]
|
||||
strlb r1, [r1]
|
||||
strlb r14, [r14]
|
||||
strlh r0, [r0]
|
||||
strlh r1, [r1]
|
||||
strlh r14, [r14]
|
||||
strl r0, [r0]
|
||||
strl r1, [r1]
|
||||
strl r14, [r14]
|
||||
strlexb r0, r1, [r14]
|
||||
strlexb r1, r14, [r0]
|
||||
strlexb r14, r0, [r1]
|
||||
strlexh r0, r1, [r14]
|
||||
strlexh r1, r14, [r0]
|
||||
strlexh r14, r0, [r1]
|
||||
strlex r0, r1, [r14]
|
||||
strlex r1, r14, [r0]
|
||||
strlex r14, r0, [r1]
|
||||
strlexd r0, r2, r3, [r14]
|
||||
strlexd r1, r12, r13, [r0]
|
||||
strlexd r14, r0, r1, [r1]
|
||||
ldrab r0, [r0]
|
||||
ldrab r1, [r1]
|
||||
ldrab r14, [r14]
|
||||
ldrah r0, [r0]
|
||||
ldrah r1, [r1]
|
||||
ldrah r14, [r14]
|
||||
ldra r0, [r0]
|
||||
ldra r1, [r1]
|
||||
ldra r14, [r14]
|
||||
ldraexb r0, [r0]
|
||||
ldraexb r1, [r1]
|
||||
ldraexb r14, [r14]
|
||||
ldraexh r0, [r0]
|
||||
ldraexh r1, [r1]
|
||||
ldraexh r14, [r14]
|
||||
ldraex r0, [r0]
|
||||
ldraex r1, [r1]
|
||||
ldraex r14, [r14]
|
||||
ldraexd r0, r1, [r0]
|
||||
ldraexd r2, r3, [r1]
|
||||
ldraexd r12, r13, [r14]
|
||||
|
||||
.thumb
|
||||
.thumb_func
|
||||
@ -20,3 +62,45 @@ bar:
|
||||
dcps3
|
||||
hlt 0
|
||||
hlt 63
|
||||
strlb r0, [r0]
|
||||
strlb r1, [r1]
|
||||
strlb r14, [r14]
|
||||
strlh r0, [r0]
|
||||
strlh r1, [r1]
|
||||
strlh r14, [r14]
|
||||
strl r0, [r0]
|
||||
strl r1, [r1]
|
||||
strl r14, [r14]
|
||||
strlexb r0, r1, [r14]
|
||||
strlexb r1, r14, [r0]
|
||||
strlexb r14, r0, [r1]
|
||||
strlexh r0, r1, [r14]
|
||||
strlexh r1, r14, [r0]
|
||||
strlexh r14, r0, [r1]
|
||||
strlex r0, r1, [r14]
|
||||
strlex r1, r14, [r0]
|
||||
strlex r14, r0, [r1]
|
||||
strlexd r0, r1, r1, [r14]
|
||||
strlexd r1, r14, r14, [r0]
|
||||
strlexd r14, r0, r0, [r1]
|
||||
ldrab r0, [r0]
|
||||
ldrab r1, [r1]
|
||||
ldrab r14, [r14]
|
||||
ldrah r0, [r0]
|
||||
ldrah r1, [r1]
|
||||
ldrah r14, [r14]
|
||||
ldra r0, [r0]
|
||||
ldra r1, [r1]
|
||||
ldra r14, [r14]
|
||||
ldraexb r0, [r0]
|
||||
ldraexb r1, [r1]
|
||||
ldraexb r14, [r14]
|
||||
ldraexh r0, [r0]
|
||||
ldraexh r1, [r1]
|
||||
ldraexh r14, [r14]
|
||||
ldraex r0, [r0]
|
||||
ldraex r1, [r1]
|
||||
ldraex r14, [r14]
|
||||
ldraexd r0, r1, [r0]
|
||||
ldraexd r1, r14, [r1]
|
||||
ldraexd r14, r0, [r14]
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
|
||||
(thumb32_opcodes): Likewise.
|
||||
(print_arm_insn): Add support for %<>T formatter.
|
||||
|
||||
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* arm-dis.c (arm_opcodes): Add HLT.
|
||||
|
||||
@ -821,6 +821,7 @@ static const struct opcode32 neon_opcodes[] =
|
||||
%P print address for pli instruction.
|
||||
|
||||
%<bitfield>r print as an ARM register
|
||||
%<bitfield>T print as an ARM register + 1
|
||||
%<bitfield>R as %r but r15 is UNPREDICTABLE
|
||||
%<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
|
||||
%<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
|
||||
@ -852,7 +853,20 @@ static const struct opcode32 arm_opcodes[] =
|
||||
/* V8 instructions. */
|
||||
{ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
|
||||
{ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
|
||||
|
||||
{ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
|
||||
|
||||
/* Virtualization Extension instructions. */
|
||||
{ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
|
||||
@ -1425,6 +1439,20 @@ static const struct opcode32 thumb32_opcodes[] =
|
||||
/* V8 instructions. */
|
||||
{ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
|
||||
{ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
|
||||
{ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
|
||||
{ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
|
||||
|
||||
/* V7 instructions. */
|
||||
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
|
||||
@ -3397,6 +3425,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
|
||||
is_unpredictable = TRUE;
|
||||
/* Fall through. */
|
||||
case 'r':
|
||||
case 'T':
|
||||
/* We want register + 1 when decoding T. */
|
||||
if (*c == 'T')
|
||||
++value;
|
||||
|
||||
if (c[1] == 'u')
|
||||
{
|
||||
/* Eat the 'u' character. */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user