darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2025-02-16 15:40:16 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

* config/bfin-parse.y (asm_1): Better check and deal with

Browse Source 
vector and scalar Multiply 16-Bit Operands instructions.
This commit is contained in:
Jie Zhang 2006-05-25 04:07:08 +00:00
parent 314e9a4e32
commit a32054651a
2 changed files with 44 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2006-05-25 Jie Zhang <jie.zhang@analog.com>
* config/bfin-parse.y (asm_1): Better check and deal with
vector and scalar Multiply 16-Bit Operands instructions.
2006-05-24 Nick Clifton <nickc@redhat.com>
* config/tc-hppa.c: Convert to ISO C90 format.
@ -48,6 +53,7 @@
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
>>>>>>> 1.2917
2006-05-23 Jie Zhang <jie.zhang@analog.com>
* config/tc-bfin.c (bfin_start_line_hook): Bump line counters

76
gas/config/bfin-parse.y
View File

@ -1730,7 +1730,7 @@ asm_1:
$$ = DSP32MULT (0, 0, $4.mod, 0, 0,
0, 0, IS_H ($3.s0), IS_H ($3.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
}
}
| REG ASSIGN multiply_halfregs opt_mode
@ -1739,6 +1739,9 @@ asm_1:
if (!IS_DREG ($1))
return yyerror ("Dreg expected");
if (IS_EVEN ($1) && $4.MM)
return yyerror ("(M) not allowed with MAC0");
if (!IS_EVEN ($1))
{
notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
@ -1747,15 +1750,13 @@ asm_1:
IS_H ($3.s0), IS_H ($3.s1), 0, 0,
&$1, 0, &$3.s0, &$3.s1, 0);
}
else if ($4.MM == 0)
else
{
notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
$$ = DSP32MULT (0, 0, $4.mod, 0, 1,
0, 0, IS_H ($3.s0), IS_H ($3.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
else
return yyerror ("Register or mode mismatch");
}
| HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
@ -1764,57 +1765,56 @@ asm_1:
if (!IS_DREG ($1) || !IS_DREG ($6))
return yyerror ("Dregs expected");
if (!IS_HCOMPL($1, $6))
return yyerror ("Dest registers mismatch");
if (check_multiply_halfregs (&$3, &$8) < 0)
return -1;
if (IS_H ($1) && !IS_H ($6))
{
notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
"dregs_lo = multiply_halfregs opt_mode\n");
$$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
{
$$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
if ((!IS_H ($1) && $4.MM)
|| (!IS_H ($6) && $9.MM))
return yyerror ("(M) not allowed with MAC0");
notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
"dregs_lo = multiply_halfregs opt_mode\n");
if (IS_H ($1))
$$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
else
return yyerror ("Multfunc Register or mode mismatch");
$$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
{
if (!IS_DREG ($1) || !IS_DREG ($6))
return yyerror ("Dregs expected");
if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
|| (IS_EVEN ($6) && $1.regno - $6.regno != 1))
return yyerror ("Dest registers mismatch");
if (check_multiply_halfregs (&$3, &$8) < 0)
return -1;
if ((IS_EVEN ($1) && $4.MM)
|| (IS_EVEN ($6) && $9.MM))
return yyerror ("(M) not allowed with MAC0");
notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
"dregs = multiply_halfregs opt_mode\n");
if (IS_EVEN ($1))
{
if ($6.regno - $1.regno != 1 || $4.MM != 0)
return yyerror ("Dest registers or mode mismatch");
/* op1 MM mmod */
$$ = DSP32MULT (0, 0, $9.mod, 1, 1,
IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
if (IS_EVEN ($1))
$$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
else
{
if ($1.regno - $6.regno != 1)
return yyerror ("Dest registers mismatch");
$$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}
$$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
&$1, 0, &$3.s0, &$3.s1, 1);
}