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Fix problems with the implementation of the uzp1 and uzp2 instructions.
sim/aarch64/ * simulator.c (do_vec_UZP): Rewrite. sim/testsuite/sim/aarch64/ * uzp.s: New.
This commit is contained in:
Jim Wilson
parent
694b382c67
commit
a4fb5981b7
@ -1,3 +1,7 @@
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2017-01-09 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_UZP): Rewrite.
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2017-01-04 Jim Wilson <jim.wilson@linaro.org>
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* cpustate.c: Include math.h.
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@ -2958,12 +2958,10 @@ do_vec_UZP (sim_cpu *cpu)
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uint64_t val_n1 = aarch64_get_vec_u64 (cpu, vn, 0);
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uint64_t val_n2 = aarch64_get_vec_u64 (cpu, vn, 1);
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uint64_t val1 = 0;
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uint64_t val2 = 0;
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uint64_t val1;
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uint64_t val2;
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uint64_t input1 = upper ? val_n1 : val_m1;
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uint64_t input2 = upper ? val_n2 : val_m2;
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unsigned i;
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uint64_t input2 = full ? val_n2 : val_m1;
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NYI_assert (29, 24, 0x0E);
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NYI_assert (21, 21, 0);
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@ -2971,32 +2969,68 @@ do_vec_UZP (sim_cpu *cpu)
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NYI_assert (13, 10, 6);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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switch (INSTR (23, 23))
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switch (INSTR (23, 22))
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{
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case 0:
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for (i = 0; i < 8; i++)
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val1 = (val_n1 >> (upper * 8)) & 0xFFULL;
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val1 |= (val_n1 >> ((upper * 8) + 8)) & 0xFF00ULL;
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val1 |= (val_n1 >> ((upper * 8) + 16)) & 0xFF0000ULL;
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val1 |= (val_n1 >> ((upper * 8) + 24)) & 0xFF000000ULL;
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val1 |= (input2 << (32 - (upper * 8))) & 0xFF00000000ULL;
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val1 |= (input2 << (24 - (upper * 8))) & 0xFF0000000000ULL;
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val1 |= (input2 << (16 - (upper * 8))) & 0xFF000000000000ULL;
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val1 |= (input2 << (8 - (upper * 8))) & 0xFF00000000000000ULL;
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if (full)
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{
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val1 |= (input1 >> (i * 8)) & (0xFFULL << (i * 8));
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val2 |= (input2 >> (i * 8)) & (0xFFULL << (i * 8));
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val2 = (val_m1 >> (upper * 8)) & 0xFFULL;
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val2 |= (val_m1 >> ((upper * 8) + 8)) & 0xFF00ULL;
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val2 |= (val_m1 >> ((upper * 8) + 16)) & 0xFF0000ULL;
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val2 |= (val_m1 >> ((upper * 8) + 24)) & 0xFF000000ULL;
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val2 |= (val_m2 << (32 - (upper * 8))) & 0xFF00000000ULL;
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val2 |= (val_m2 << (24 - (upper * 8))) & 0xFF0000000000ULL;
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val2 |= (val_m2 << (16 - (upper * 8))) & 0xFF000000000000ULL;
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val2 |= (val_m2 << (8 - (upper * 8))) & 0xFF00000000000000ULL;
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}
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break;
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case 1:
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for (i = 0; i < 4; i++)
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val1 = (val_n1 >> (upper * 16)) & 0xFFFFULL;
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val1 |= (val_n1 >> ((upper * 16) + 16)) & 0xFFFF0000ULL;
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val1 |= (input2 << (32 - (upper * 16))) & 0xFFFF00000000ULL;;
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val1 |= (input2 << (16 - (upper * 16))) & 0xFFFF000000000000ULL;
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if (full)
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{
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val1 |= (input1 >> (i * 16)) & (0xFFFFULL << (i * 16));
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val2 |= (input2 >> (i * 16)) & (0xFFFFULL << (i * 16));
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val2 = (val_m1 >> (upper * 16)) & 0xFFFFULL;
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val2 |= (val_m1 >> ((upper * 16) + 16)) & 0xFFFF0000ULL;
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val2 |= (val_m2 << (32 - (upper * 16))) & 0xFFFF00000000ULL;
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val2 |= (val_m2 << (16 - (upper * 16))) & 0xFFFF000000000000ULL;
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}
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break;
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case 2:
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val1 = ((input1 & 0xFFFFFFFF) | ((input1 >> 32) & 0xFFFFFFFF00000000ULL));
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val2 = ((input2 & 0xFFFFFFFF) | ((input2 >> 32) & 0xFFFFFFFF00000000ULL));
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val1 = (val_n1 >> (upper * 32)) & 0xFFFFFFFF;
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val1 |= (input2 << (32 - (upper * 32))) & 0xFFFFFFFF00000000ULL;
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if (full)
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{
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val2 = (val_m1 >> (upper * 32)) & 0xFFFFFFFF;
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val2 |= (val_m2 << (32 - (upper * 32))) & 0xFFFFFFFF00000000ULL;
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}
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break;
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case 3:
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val1 = input1;
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val2 = input2;
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break;
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if (! full)
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HALT_UNALLOC;
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val1 = upper ? val_n2 : val_n1;
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val2 = upper ? val_m2 : val_m1;
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break;
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}
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aarch64_set_vec_u64 (cpu, vd, 0, val1);
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@ -1,3 +1,7 @@
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2017-01-09 Jim Wilson <jim.wilson@linaro.org>
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* uzp.s: New.
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2017-01-04 Jim Wilson <jim.wilson@linaro.org>
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* fcsel.s: New.
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214
sim/testsuite/sim/aarch64/uzp.s
Normal file
214
sim/testsuite/sim/aarch64/uzp.s
Normal file
@ -0,0 +1,214 @@
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# mach: aarch64
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# Check the unzip instructions: uzp1, uzp2.
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.include "testutils.inc"
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input1:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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input2:
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.word 0x14131211
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.word 0x18171615
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.word 0x1c1b1a19
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.word 0x201f1e1d
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zl8b:
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.word 0x07050301
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.word 0x17151311
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zu8b:
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.word 0x08060402
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.word 0x18161412
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zl16b:
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.word 0x07050301
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.word 0x0f0d0b09
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.word 0x17151311
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.word 0x1f1d1b19
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zu16b:
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.word 0x08060402
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.word 0x100e0c0a
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.word 0x18161412
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.word 0x201e1c1a
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zl4h:
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.word 0x06050201
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.word 0x16151211
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zu4h:
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.word 0x08070403
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.word 0x18171413
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zl8h:
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.word 0x06050201
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.word 0x0e0d0a09
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.word 0x16151211
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.word 0x1e1d1a19
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zu8h:
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.word 0x08070403
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.word 0x100f0c0b
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.word 0x18171413
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.word 0x201f1c1b
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zl2s:
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.word 0x04030201
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.word 0x14131211
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zu2s:
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.word 0x08070605
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.word 0x18171615
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zl4s:
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.word 0x04030201
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.word 0x0c0b0a09
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.word 0x14131211
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.word 0x1c1b1a19
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zu4s:
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.word 0x08070605
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.word 0x100f0e0d
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.word 0x18171615
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.word 0x201f1e1d
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zl2d:
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.word 0x04030201
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.word 0x08070605
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.word 0x14131211
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.word 0x18171615
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zu2d:
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.word 0x0c0b0a09
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.word 0x100f0e0d
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.word 0x1c1b1a19
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.word 0x201f1e1d
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start
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adrp x0, input1
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ldr q0, [x0, #:lo12:input1]
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adrp x0, input2
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ldr q1, [x0, #:lo12:input2]
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uzp1 v2.8b, v0.8b, v1.8b
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mov x1, v2.d[0]
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adrp x3, zl8b
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ldr x4, [x3, #:lo12:zl8b]
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cmp x1, x4
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bne .Lfailure
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uzp2 v2.8b, v0.8b, v1.8b
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mov x1, v2.d[0]
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adrp x3, zu8b
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ldr x4, [x3, #:lo12:zu8b]
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cmp x1, x4
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bne .Lfailure
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uzp1 v2.16b, v0.16b, v1.16b
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl16b
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ldr x4, [x3, #:lo12:zl16b]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl16b+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.16b, v0.16b, v1.16b
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu16b
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ldr x4, [x3, #:lo12:zu16b]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu16b+8]
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cmp x2, x5
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bne .Lfailure
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uzp1 v2.4h, v0.4h, v1.4h
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mov x1, v2.d[0]
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adrp x3, zl4h
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ldr x4, [x3, #:lo12:zl4h]
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cmp x1, x4
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bne .Lfailure
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uzp2 v2.4h, v0.4h, v1.4h
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mov x1, v2.d[0]
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adrp x3, zu4h
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ldr x4, [x3, #:lo12:zu4h]
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cmp x1, x4
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bne .Lfailure
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uzp1 v2.8h, v0.8h, v1.8h
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl8h
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ldr x4, [x3, #:lo12:zl8h]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl8h+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.8h, v0.8h, v1.8h
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu8h
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ldr x4, [x3, #:lo12:zu8h]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu8h+8]
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cmp x2, x5
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bne .Lfailure
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uzp1 v2.2s, v0.2s, v1.2s
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mov x1, v2.d[0]
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adrp x3, zl2s
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ldr x4, [x3, #:lo12:zl2s]
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cmp x1, x4
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bne .Lfailure
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uzp2 v2.2s, v0.2s, v1.2s
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mov x1, v2.d[0]
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adrp x3, zu2s
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ldr x4, [x3, #:lo12:zu2s]
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cmp x1, x4
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bne .Lfailure
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uzp1 v2.4s, v0.4s, v1.4s
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl4s
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ldr x4, [x3, #:lo12:zl4s]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl4s+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.4s, v0.4s, v1.4s
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu4s
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ldr x4, [x3, #:lo12:zu4s]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu4s+8]
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cmp x2, x5
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bne .Lfailure
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uzp1 v2.2d, v0.2d, v1.2d
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl2d
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ldr x4, [x3, #:lo12:zl2d]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl2d+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.2d, v0.2d, v1.2d
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu2d
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ldr x4, [x3, #:lo12:zu2d]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu2d+8]
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cmp x2, x5
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bne .Lfailure
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pass
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.Lfailure:
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fail
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