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PR 17947: Add -> to indicate two instructions are explicitly serial
This commit is contained in:
Michael Meissner
parent
8c811b9d07
commit
a561cd980b
@ -1,3 +1,10 @@
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1998-10-26 Michael Meissner <meissner@cygnus.com>
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* config/tc-m32r.c (assemble_two_insns): Rename assemble_two_insns
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from assemble_parallel_insns. Add support for '->' to indicate
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explicitly serializing the instructions.
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(md_assemble): Ditto.
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Sat Oct 24 15:12:19 1998 Catherine Moore <clm@cygnus.com>
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* config/tc-sh.c (sh_fix_adjustable): Adjust EXTERN and
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@ -43,10 +43,12 @@ typedef struct
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const CGEN_INSN * insn;
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const CGEN_INSN * orig_insn;
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CGEN_FIELDS fields;
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#ifdef CGEN_INT_INSN
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cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
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#if CGEN_INT_INSN_P
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CGEN_INSN_INT buffer [1];
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#define INSN_VALUE(buf) (*(buf))
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#else
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char buffer [CGEN_MAX_INSN_SIZE];
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unsigned char buffer [CGEN_MAX_INSN_SIZE];
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#define INSN_VALUE(buf) (buf)
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#endif
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char * addr;
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fragS * frag;
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@ -703,54 +705,44 @@ can_make_parallel (a, b)
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return NULL;
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}
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#ifdef CGEN_INT_INSN
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/* Force the top bit of the second 16-bit insn to be set. */
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static void
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make_parallel (buffer)
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cgen_insn_t * buffer;
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CGEN_INSN_BYTES_PTR buffer;
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{
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/* Force the top bit of the second insn to be set. */
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bfd_vma value;
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if (CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG)
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{
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value = bfd_getb16 ((bfd_byte *) buffer);
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value |= 0x8000;
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bfd_putb16 (value, (char *) buffer);
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}
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else
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{
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value = bfd_getl16 ((bfd_byte *) buffer);
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value |= 0x8000;
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bfd_putl16 (value, (char *) buffer);
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}
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#if CGEN_INT_INSN_P
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*buffer |= 0x8000;
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#else
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buffer [CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
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|= 0x80;
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#endif
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}
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#else
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/* Same as make_parallel except buffer contains the bytes in target order. */
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static void
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make_parallel (buffer)
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char * buffer;
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target_make_parallel (buffer)
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char *buffer;
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{
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/* Force the top bit of the second insn to be set. */
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buffer [CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
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|= 0x80;
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}
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#endif /* ! CGEN_INT_INSN */
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/* Assemble two instructions with an explicit parallel operation (||) or
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sequential operation (->). */
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static void
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assemble_parallel_insn (str, str2)
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assemble_two_insns (str, str2, parallel_p)
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char * str;
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char * str2;
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int parallel_p;
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{
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char * str3;
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m32r_insn first;
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m32r_insn second;
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char * errmsg;
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char save_str2 = *str2;
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* str2 = 0; /* Seperate the two instructions. */
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/* If there was a previous 16 bit insn, then fill the following 16 bit slot,
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@ -786,14 +778,14 @@ assemble_parallel_insn (str, str2)
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}
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/* Check to see if this is an allowable parallel insn. */
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if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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if (parallel_p && CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' cannot be executed in parallel."), str);
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return;
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}
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*str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
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*str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */
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str3 = str; /* Save the original string pointer. */
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str = str2 + 2; /* Advanced past the parsed string. */
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str2 = str3; /* Remember the entire string in case it is needed for error messages. */
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@ -829,11 +821,11 @@ assemble_parallel_insn (str, str2)
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may have to change. */
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first.orig_insn = first.insn;
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first.insn = m32r_cgen_lookup_get_insn_operands
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(gas_cgen_opcode_desc, NULL, bfd_getb16 ((char *) first.buffer), 16,
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(gas_cgen_opcode_desc, NULL, INSN_VALUE (first.buffer), 16,
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first.indices);
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if (first.insn == NULL)
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as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
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as_fatal (_("internal error: lookup/get operands failed"));
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second.debug_sym_link = NULL;
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@ -862,14 +854,14 @@ assemble_parallel_insn (str, str2)
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}
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/* Check to see if this is an allowable parallel insn. */
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if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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if (parallel_p && CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' cannot be executed in parallel."), str);
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return;
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}
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if (! enable_m32rx)
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if (parallel_p && ! enable_m32rx)
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{
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if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
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&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
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@ -883,11 +875,11 @@ assemble_parallel_insn (str, str2)
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/* Get the indices of the operands of the instruction. */
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second.orig_insn = second.insn;
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second.insn = m32r_cgen_lookup_get_insn_operands
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(gas_cgen_opcode_desc, NULL, bfd_getb16 ((char *) second.buffer), 16,
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(gas_cgen_opcode_desc, NULL, INSN_VALUE (second.buffer), 16,
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second.indices);
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if (second.insn == NULL)
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as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
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as_fatal (_("internal error: lookup/get operands failed"));
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/* We assume that if the first instruction writes to a register that is
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read by the second instruction it is because the programmer intended
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@ -897,7 +889,7 @@ assemble_parallel_insn (str, str2)
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a warning message. Similarly we assume that parallel branch and jump
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instructions are deliberate and should not produce errors. */
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if (warn_explicit_parallel_conflicts)
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if (parallel_p && warn_explicit_parallel_conflicts)
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{
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if (first_writes_to_seconds_operands (& first, & second, false))
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/* xgettext:c-format */
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@ -908,7 +900,7 @@ assemble_parallel_insn (str, str2)
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as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
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}
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if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
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if (!parallel_p || (errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
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{
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/* Get the fixups for the first instruction. */
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gas_cgen_swap_fixups ();
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@ -919,7 +911,8 @@ assemble_parallel_insn (str, str2)
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CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
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/* Force the top bit of the second insn to be set. */
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make_parallel (second.buffer);
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if (parallel_p)
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make_parallel (second.buffer);
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/* Get its fixups. */
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gas_cgen_restore_fixups ();
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@ -977,7 +970,14 @@ md_assemble (str)
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/* Look for a parallel instruction seperator. */
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if ((str2 = strstr (str, "||")) != NULL)
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{
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assemble_parallel_insn (str, str2);
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assemble_two_insns (str, str2, 1);
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return;
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}
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/* Also look for a sequential instruction seperator. */
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if ((str2 = strstr (str, "->")) != NULL)
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{
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assemble_two_insns (str, str2, 0);
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return;
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}
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/* end-sanitize-m32rx */
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@ -1045,11 +1045,11 @@ md_assemble (str)
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/* Get the indices of the operands of the instruction.
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FIXME: See assemble_parallel for notes on orig_insn. */
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insn.insn = m32r_cgen_lookup_get_insn_operands
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(gas_cgen_opcode_desc, NULL, bfd_getb16 ((char *) insn.buffer),
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(gas_cgen_opcode_desc, NULL, INSN_VALUE (insn.buffer),
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16, insn.indices);
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if (insn.insn == NULL)
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as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
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as_fatal (_("internal error: lookup/get operands failed"));
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}
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/* end-sanitize-m32rx */
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@ -1113,7 +1113,7 @@ md_assemble (str)
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SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
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SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
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make_parallel (insn.addr);
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target_make_parallel (insn.addr);
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/* Swap any relaxable frags recorded for the two insns. */
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/* FIXME: Clarify. relaxation precludes parallel insns */
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