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include/opcodes/
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
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@ -1,3 +1,8 @@
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2006-05-25 Richard Sandiford <richard@codesourcery.com>
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* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
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* gas/m68k/mcf-fpu.d: Adjust accordingly.
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2006-05-25 Jie Zhang <jie.zhang@analog.com>
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* gas/bfin/vector2.s, gas/bfin/vector2.d: Test to ensure (m) is not
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@ -168,3 +168,11 @@ Disassembly of section .text:
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[ 0-9a-f]+: f22e 5038 0008 fcmpw %fp@\(8\),%fp0
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[ 0-9a-f]+: f22e 5438 0008 fcmpd %fp@\(8\),%fp0
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[ 0-9a-f]+: f22e 5838 0008 fcmpb %fp@\(8\),%fp0
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[ 0-9a-f]+: f22e f0f2 0008 fmovemd %fp0-%fp3/%fp6,%fp@\(8\)
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[ 0-9a-f]+: f22e d02c 0008 fmovemd %fp@\(8\),%fp2/%fp4-%fp5
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[ 0-9a-f]+: f22e f027 0008 fmovemd %fp2/%fp5-%fp7,%fp@\(8\)
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[ 0-9a-f]+: f22e d0e1 0008 fmovemd %fp@\(8\),%fp0-%fp2/%fp7
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[ 0-9a-f]+: f22e f0f2 0008 fmovemd %fp0-%fp3/%fp6,%fp@\(8\)
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[ 0-9a-f]+: f22e d02c 0008 fmovemd %fp@\(8\),%fp2/%fp4-%fp5
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[ 0-9a-f]+: f22e f027 0008 fmovemd %fp2/%fp5-%fp7,%fp@\(8\)
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[ 0-9a-f]+: f22e d0e1 0008 fmovemd %fp@\(8\),%fp0-%fp2/%fp7
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@ -163,3 +163,11 @@
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fcmpw %fp@(8),%fp0
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fcmpd %fp@(8),%fp0
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fcmpb %fp@(8),%fp0
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fmovemd %fp0-%fp3/%fp6,%fp@(8)
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fmovemd %fp@(8),%fp5/%fp4/%fp2
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fmovemd #0x27,%fp@(8)
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fmovemd %fp@(8),#0xe1
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fmovem %fp0-%fp3/%fp6,%fp@(8)
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fmovem %fp@(8),%fp5/%fp4/%fp2
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fmovem #0x27,%fp@(8)
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fmovem %fp@(8),#0xe1
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@ -1,3 +1,7 @@
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2006-05-25 Richard Sandiford <richard@codesourcery.com>
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* m68k.h (mcf_mask): Define.
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2006-05-05 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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@ -42,6 +42,7 @@
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#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
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#define mcfisa_b 0x8000 /* ColdFire ISA_B. */
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#define mcfusp 0x10000 /* ColdFire USP instructions. */
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#define mcf_mask 0x1f200
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/* Handy aliases. */
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#define m68040up (m68040 | m68060)
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@ -1,3 +1,14 @@
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2006-05-25 Richard Sandiford <richard@codesourcery.com>
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* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
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and fmovem entries. Put register list entries before immediate
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mask entries. Use "l" rather than "L" in the fmovem entries.
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* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
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out from INFO.
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(m68k_scan_mask): New function, split out from...
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(print_insn_m68k): ...here. If no architecture has been set,
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first try printing an m680x0 instruction, then try a Coldfire one.
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2006-05-24 Nick Clifton <nickc@redhat.com>
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* po/ga.po: Updated Irish translation.
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@ -1204,13 +1204,13 @@ print_insn_arg (const char *d,
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static int
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match_insn_m68k (bfd_vma memaddr,
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disassemble_info * info,
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const struct m68k_opcode * best,
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struct private * priv)
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const struct m68k_opcode * best)
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{
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unsigned char *save_p;
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unsigned char *p;
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const char *d;
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struct private *priv = (struct private *) info->private_data;
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bfd_byte *buffer = priv->the_buffer;
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fprintf_ftype save_printer = info->fprintf_func;
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void (* save_print_address) (bfd_vma, struct disassemble_info *)
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@ -1343,21 +1343,24 @@ match_insn_m68k (bfd_vma memaddr,
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return p - buffer;
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}
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/* Print the m68k instruction at address MEMADDR in debugged memory,
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on INFO->STREAM. Returns length of the instruction, in bytes. */
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/* Try to interpret the instruction at address MEMADDR as one that
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can execute on a processor with the features given by ARCH_MASK.
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If successful, print the instruction to INFO->STREAM and return
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its length in bytes. Return 0 otherwise. */
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int
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print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
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static int
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m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
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unsigned int arch_mask)
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{
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int i;
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const char *d;
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unsigned int arch_mask;
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struct private priv;
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bfd_byte *buffer = priv.the_buffer;
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int major_opcode;
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static int numopcodes[16];
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static const struct m68k_opcode **opcodes[16];
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static int numopcodes[16];
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int val;
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int major_opcode;
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struct private *priv = (struct private *) info->private_data;
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bfd_byte *buffer = priv->the_buffer;
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if (!opcodes[0])
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{
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@ -1385,23 +1388,6 @@ print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
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*opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
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}
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info->private_data = (PTR) &priv;
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/* Tell objdump to use two bytes per chunk
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and six bytes per line for displaying raw data. */
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info->bytes_per_chunk = 2;
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info->bytes_per_line = 6;
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info->display_endian = BFD_ENDIAN_BIG;
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priv.max_fetched = priv.the_buffer;
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priv.insn_start = memaddr;
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if (setjmp (priv.bailout) != 0)
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/* Error return. */
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return -1;
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arch_mask = bfd_m68k_mach_to_features (info->mach);
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if (!arch_mask)
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arch_mask = ~(unsigned int)0;
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FETCH_DATA (info, buffer + 2);
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major_opcode = (buffer[0] >> 4) & 15;
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@ -1467,10 +1453,57 @@ print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
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}
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if (*d == '\0')
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if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
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if ((val = match_insn_m68k (memaddr, info, opc)))
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return val;
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}
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}
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return 0;
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}
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/* Print the m68k instruction at address MEMADDR in debugged memory,
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on INFO->STREAM. Returns length of the instruction, in bytes. */
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int
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print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
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{
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unsigned int arch_mask;
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struct private priv;
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int val;
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bfd_byte *buffer = priv.the_buffer;
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info->private_data = (PTR) &priv;
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/* Tell objdump to use two bytes per chunk
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and six bytes per line for displaying raw data. */
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info->bytes_per_chunk = 2;
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info->bytes_per_line = 6;
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info->display_endian = BFD_ENDIAN_BIG;
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priv.max_fetched = priv.the_buffer;
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priv.insn_start = memaddr;
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if (setjmp (priv.bailout) != 0)
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/* Error return. */
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return -1;
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arch_mask = bfd_m68k_mach_to_features (info->mach);
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if (!arch_mask)
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{
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/* First try printing an m680x0 instruction. Try printing a Coldfire
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one if that fails. */
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val = m68k_scan_mask (memaddr, info, m68k_mask);
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if (val)
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return val;
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val = m68k_scan_mask (memaddr, info, mcf_mask);
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if (val)
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return val;
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}
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else
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{
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val = m68k_scan_mask (memaddr, info, arch_mask);
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if (val)
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return val;
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}
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/* Handle undefined instructions. */
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info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
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@ -913,10 +913,10 @@ const struct m68k_opcode m68k_opcodes[] =
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{"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat },
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{"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizsl3", cfloat },
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{"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
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{"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
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{"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Iil3ys", cfloat },
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{"fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat },
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{"fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat },
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{"fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat },
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{"fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat },
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{"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
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{"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
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@ -938,10 +938,10 @@ const struct m68k_opcode m68k_opcodes[] =
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target is a single %fpiar. */
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{"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat },
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{"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "IizsL3", cfloat },
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{"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
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{"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
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{"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "IiL3ys", cfloat },
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{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat },
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{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat },
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{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat },
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{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat },
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{"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
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{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
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