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Clean up more tracing.
FIX interrupt delivery - was zapping PSW before it had been saved. FIX interrupt return, was one instruction out.
This commit is contained in:
Andrew Cagney
parent
175c6fd375
commit
a72f8fb439
@ -1,3 +1,15 @@
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Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* simops.c: Move "mov", "reti", to v850.igen, fix tracing.
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* interp.c (hash): Delete.
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* v850.igen (nop): Really do nothing.
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* interp.c (do_interrupt): Mask interrupts after PSW is saved, not
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before.
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* v850.igen (reti): Return to current PC not previous.
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start-sanitize-v850e
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Wed Sep 17 14:02:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
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@ -66,151 +66,117 @@ do_interrupt (sd, data)
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char **interrupt_name = (char**)data;
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enum interrupt_type inttype;
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inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
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/* Disable further interrupts. */
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PSW |= PSW_ID;
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/* Indicate that we're doing interrupt not exception processing. */
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PSW &= ~PSW_EP;
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/* For a hardware reset, drop everything and jump to the start
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address */
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if (inttype == int_reset)
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{
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PC = 0;
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PSW = 0x20;
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ECR = 0;
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/* (Might be useful to init other regs with random values.) */
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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else if (inttype == int_nmi)
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/* Deliver an NMI when allowed */
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if (inttype == int_nmi)
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{
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if (PSW & PSW_NP)
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{
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/* We're already working on an NMI, so this one must wait
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around until the previous one is done. The processor
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ignores subsequent NMIs, so we don't need to count them. */
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State.pending_nmi = 1;
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ignores subsequent NMIs, so we don't need to count them.
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Just keep re-scheduling a single NMI until it manages to
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be delivered */
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if (STATE_CPU (sd, 0)->pending_nmi != NULL)
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sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
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STATE_CPU (sd, 0)->pending_nmi =
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sim_events_schedule (sd, 1, do_interrupt, data);
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return;
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}
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else
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{
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/* NMI can be delivered. Do not deschedule pending_nmi as
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that, if still in the event queue, is a second NMI that
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needs to be delivered later. */
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FEPC = PC;
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FEPSW = PSW;
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/* Set the FECC part of the ECR. */
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ECR &= 0x0000ffff;
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ECR |= 0x10;
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PSW |= PSW_NP;
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PSW &= ~PSW_EP;
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PSW |= PSW_ID;
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PC = 0x10;
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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}
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else
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/* deliver maskable interrupt when allowed */
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if (inttype > int_nmi && inttype < num_int_types)
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{
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EIPC = PC;
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EIPSW = PSW;
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/* Clear the EICC part of the ECR, will set below. */
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ECR &= 0xffff0000;
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switch (inttype)
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if ((PSW & PSW_NP) || (PSW & PSW_ID))
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{
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case int_intov1:
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PC = 0x80;
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ECR |= 0x80;
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break;
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case int_intp10:
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PC = 0x90;
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ECR |= 0x90;
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break;
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case int_intp11:
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PC = 0xa0;
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ECR |= 0xa0;
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break;
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case int_intp12:
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PC = 0xb0;
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ECR |= 0xb0;
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break;
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case int_intp13:
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PC = 0xc0;
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ECR |= 0xc0;
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break;
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case int_intcm4:
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PC = 0xd0;
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ECR |= 0xd0;
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break;
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default:
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/* Should never be possible. */
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abort ();
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break;
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/* Can't deliver this interrupt, reschedule it for later */
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sim_events_schedule (sd, 1, do_interrupt, data);
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return;
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}
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else
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{
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/* save context */
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EIPC = PC;
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EIPSW = PSW;
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/* Disable further interrupts. */
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PSW |= PSW_ID;
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/* Indicate that we're doing interrupt not exception processing. */
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PSW &= ~PSW_EP;
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/* Clear the EICC part of the ECR, will set below. */
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ECR &= 0xffff0000;
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switch (inttype)
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{
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case int_intov1:
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PC = 0x80;
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ECR |= 0x80;
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break;
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case int_intp10:
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PC = 0x90;
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ECR |= 0x90;
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break;
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case int_intp11:
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PC = 0xa0;
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ECR |= 0xa0;
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break;
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case int_intp12:
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PC = 0xb0;
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ECR |= 0xb0;
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break;
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case int_intp13:
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PC = 0xc0;
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ECR |= 0xc0;
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break;
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case int_intcm4:
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PC = 0xd0;
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ECR |= 0xd0;
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break;
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default:
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/* Should never be possible. */
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sim_engine_abort (sd, NULL, NULL_CIA,
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"do_interrupt - internal error - bad switch");
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break;
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}
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}
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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/* some other interrupt? */
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sim_engine_abort (sd, NULL, NULL_CIA,
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"do_interrupt - internal error - interrupt %d unknown",
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inttype);
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}
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/* These default values correspond to expected usage for the chip. */
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int v850_debug;
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uint32 OP[4];
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static long hash PARAMS ((long));
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#if 0
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static void do_format_1_2 PARAMS ((uint32));
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static void do_format_3 PARAMS ((uint32));
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static void do_format_4 PARAMS ((uint32));
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static void do_format_5 PARAMS ((uint32));
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static void do_format_6 PARAMS ((uint32));
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static void do_format_7 PARAMS ((uint32));
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static void do_format_8 PARAMS ((uint32));
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static void do_format_9_10 PARAMS ((uint32));
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#endif
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#define MAX_HASH 63
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struct hash_entry
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{
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struct hash_entry *next;
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unsigned long opcode;
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unsigned long mask;
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struct simops *ops;
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};
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struct hash_entry hash_table[MAX_HASH+1];
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static INLINE long
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hash(insn)
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long insn;
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{
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if ( (insn & 0x0600) == 0
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|| (insn & 0x0700) == 0x0200
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|| (insn & 0x0700) == 0x0600
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|| (insn & 0x0780) == 0x0700)
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return (insn & 0x07e0) >> 5;
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if ((insn & 0x0700) == 0x0300
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|| (insn & 0x0700) == 0x0400
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|| (insn & 0x0700) == 0x0500)
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return (insn & 0x0780) >> 7;
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if ((insn & 0x07c0) == 0x0780)
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return (insn & 0x07c0) >> 6;
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return (insn & 0x07e0) >> 5;
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}
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#if 0
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static struct hash_entry *
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lookup_hash (sd, ins)
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SIM_DESC sd;
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uint32 ins;
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{
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struct hash_entry *h;
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h = &hash_table[hash(ins)];
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while ((ins & h->mask) != h->opcode)
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{
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if (h->next == NULL)
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{
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sim_io_error (sd, "ERROR looking up hash for 0x%lx, PC=0x%lx",
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(long) ins, (long) PC);
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}
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h = h->next;
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}
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return (h);
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}
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#endif
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SIM_DESC
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sim_open (kind, cb, abfd, argv)
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@ -329,66 +295,6 @@ sim_stop (sd)
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return 0;
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}
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#if 0
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void
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sim_engine_run (sd, next_cpu_nr, siggnal)
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SIM_DESC sd;
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int next_cpu_nr;
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int siggnal;
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{
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uint32 inst;
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SIM_ADDR oldpc;
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while (1)
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{
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struct hash_entry * h;
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/* Fetch the current instruction. */
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inst = RLW (PC);
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oldpc = PC;
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h = lookup_hash (sd, inst);
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OP[0] = inst & 0x1f;
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OP[1] = (inst >> 11) & 0x1f;
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OP[2] = (inst >> 16) & 0xffff;
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OP[3] = inst;
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/* fprintf (stderr, "PC = %x, SP = %x\n", PC, SP ); */
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if (inst == 0)
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{
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fprintf (stderr, "NOP encountered!\n");
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break;
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}
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PC += h->ops->func ();
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if (oldpc == PC)
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{
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sim_io_eprintf (sd, "simulator loop at %lx\n", (long) PC );
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break;
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}
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if (sim_events_tick (sd))
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{
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sim_events_process (sd);
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}
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}
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}
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#endif
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#if 0
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int
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sim_trace (sd)
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SIM_DESC sd;
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{
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#ifdef DEBUG
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v850_debug = DEBUG;
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#endif
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sim_resume (sd, 0, 0);
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return 1;
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}
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#endif
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void
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sim_info (sd, verbose)
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SIM_DESC sd;
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@ -41,7 +41,6 @@ typedef struct _v850_regs {
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reg_t sregs[32]; /* system registers, including psw */
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reg_t pc;
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int dummy_mem; /* where invalid accesses go */
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int pending_nmi;
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} v850_regs;
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struct _sim_cpu
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@ -49,6 +48,7 @@ struct _sim_cpu
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/* ... simulator specific members ... */
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v850_regs reg;
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reg_t psw_mask; /* only allow non-reserved bits to be set */
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sim_event *pending_nmi;
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/* ... base type ... */
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sim_cpu_base base;
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};
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@ -1330,19 +1330,6 @@ OP_160 ()
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return 2;
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}
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/* mov reg, reg */
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int
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OP_0 ()
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{
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trace_input ("mov", OP_REG_REG_MOVE, 0);
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State.regs[ OP[1] ] = State.regs[ OP[0] ];
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trace_output (OP_REG_REG_MOVE);
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return 2;
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}
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/* mov sign_extend(imm5), reg */
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int
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OP_200 ()
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@ -1826,28 +1813,6 @@ OP_12007E0 ()
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return 0;
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}
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/* reti */
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int
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OP_14007E0 ()
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{
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trace_input ("reti", OP_NONE, 0);
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trace_output (OP_NONE);
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/* Restore for NMI if only NP on, otherwise is interrupt or exception. */
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if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
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{
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PC = FEPC - 4;
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PSW = FEPSW;
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}
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else
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{
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PC = EIPC - 4;
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PSW = EIPSW;
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}
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return 0;
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}
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/* trap */
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int
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OP_10007E0 ()
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@ -631,9 +631,12 @@ regID,111111,RRRRR + 0000000000100000:IX:::ldsr
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rrrrr!0,000000,RRRRR:I:::mov
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"mov r<reg1>, r<reg2>"
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{
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COMPAT_1 (OP_0 ());
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TRACE_ALU_INPUT0 ();
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GR[reg2] = GR[reg1];
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TRACE_ALU_RESULT (GR[reg2]);
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}
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rrrrr!0,010000,iiiii:II:::mov
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"mov <imm5>, r<reg2>"
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{
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@ -757,7 +760,7 @@ rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
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0000000000000000:I:::nop
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"nop"
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{
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COMPAT_1 (OP_0 ());
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/* do nothing, trace nothing */
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}
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@ -886,7 +889,22 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
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0000011111100000 + 0000000101000000:X:::reti
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"reti"
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{
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COMPAT_2 (OP_14007E0 ());
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if ((PSW & PSW_EP))
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{
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nia = (EIPC & ~1);
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PSW = EIPSW;
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}
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else if ((PSW & PSW_NP))
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{
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nia = (FEPC & ~1);
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PSW = FEPSW;
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}
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else
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{
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nia = (EIPC & ~1);
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PSW = EIPSW;
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}
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TRACE_BRANCH1 (PSW);
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}
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