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2005-02-11 Jan Beulich <jbeulich@novell.com> * config/tc-ia64.c (md): Remove last_groups and group_idx. (errata_nop_necessary_p): Remove declaraction and definition. (emit_one_bundle): Don't call errata_nop_necessary_p. Don't update md.group_idx. Don't reset md.last_groups.
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Jan Beulich
parent
b3f19c14d0
commit
a911c10a55
@ -1,3 +1,10 @@
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2005-02-11 Jan Beulich <jbeulich@novell.com>
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* config/tc-ia64.c (md): Remove last_groups and group_idx.
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(errata_nop_necessary_p): Remove declaraction and definition.
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(emit_one_bundle): Don't call errata_nop_necessary_p. Don't
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update md.group_idx. Don't reset md.last_groups.
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2005-02-11 Jan Beulich <jbeulich@novell.com>
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* config/tc-ia64.c (parse_section_name): Handle non-quoted first
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@ -292,25 +292,6 @@ static struct
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the current DV-checking block. */
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int maxpaths; /* size currently allocated for
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entry_labels */
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/* Support for hardware errata workarounds. */
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/* Record data about the last three insn groups. */
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struct group
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{
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/* B-step workaround.
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For each predicate register, this is set if the corresponding insn
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group conditionally sets this register with one of the affected
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instructions. */
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int p_reg_set[64];
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/* B-step workaround.
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For each general register, this is set if the corresponding insn
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a) is conditional one one of the predicate registers for which
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P_REG_SET is 1 in the corresponding entry of the previous group,
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b) sets this general register with one of the affected
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instructions. */
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int g_reg_set_conditionally[128];
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} last_groups[3];
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int group_idx;
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int pointer_size; /* size in bytes of a pointer */
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int pointer_size_shift; /* shift size of a pointer for alignment */
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@ -775,7 +756,6 @@ static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode
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expressionS *e));
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static int parse_operand PARAMS ((expressionS *e));
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static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
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static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit));
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static void build_insn PARAMS ((struct slot *, bfd_vma *));
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static void emit_one_bundle PARAMS ((void));
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static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
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@ -6136,98 +6116,6 @@ parse_operands (idesc)
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return idesc;
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}
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/* Keep track of state necessary to determine whether a NOP is necessary
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to avoid an erratum in A and B step Itanium chips, and return 1 if we
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detect a case where additional NOPs may be necessary. */
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static int
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errata_nop_necessary_p (slot, insn_unit)
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struct slot *slot;
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enum ia64_unit insn_unit;
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{
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int i;
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struct group *this_group = md.last_groups + md.group_idx;
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struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
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struct ia64_opcode *idesc = slot->idesc;
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/* Test whether this could be the first insn in a problematic sequence. */
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if (insn_unit == IA64_UNIT_F)
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{
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for (i = 0; i < idesc->num_outputs; i++)
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if (idesc->operands[i] == IA64_OPND_P1
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|| idesc->operands[i] == IA64_OPND_P2)
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{
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int regno = slot->opnd[i].X_add_number - REG_P;
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/* Ignore invalid operands; they generate errors elsewhere. */
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if (regno >= 64)
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return 0;
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this_group->p_reg_set[regno] = 1;
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}
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}
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/* Test whether this could be the second insn in a problematic sequence. */
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if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
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&& prev_group->p_reg_set[slot->qp_regno])
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{
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for (i = 0; i < idesc->num_outputs; i++)
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if (idesc->operands[i] == IA64_OPND_R1
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|| idesc->operands[i] == IA64_OPND_R2
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|| idesc->operands[i] == IA64_OPND_R3)
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{
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int regno = slot->opnd[i].X_add_number - REG_GR;
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/* Ignore invalid operands; they generate errors elsewhere. */
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if (regno >= 128)
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return 0;
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if (strncmp (idesc->name, "add", 3) != 0
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&& strncmp (idesc->name, "sub", 3) != 0
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&& strncmp (idesc->name, "shladd", 6) != 0
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&& (idesc->flags & IA64_OPCODE_POSTINC) == 0)
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this_group->g_reg_set_conditionally[regno] = 1;
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}
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}
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/* Test whether this could be the third insn in a problematic sequence. */
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for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
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{
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if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
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idesc->operands[i] == IA64_OPND_R3
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/* For mov indirect. */
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|| idesc->operands[i] == IA64_OPND_RR_R3
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|| idesc->operands[i] == IA64_OPND_DBR_R3
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|| idesc->operands[i] == IA64_OPND_IBR_R3
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|| idesc->operands[i] == IA64_OPND_PKR_R3
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|| idesc->operands[i] == IA64_OPND_PMC_R3
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|| idesc->operands[i] == IA64_OPND_PMD_R3
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|| idesc->operands[i] == IA64_OPND_MSR_R3
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|| idesc->operands[i] == IA64_OPND_CPUID_R3
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/* For itr. */
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|| idesc->operands[i] == IA64_OPND_ITR_R3
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|| idesc->operands[i] == IA64_OPND_DTR_R3
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/* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
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|| idesc->operands[i] == IA64_OPND_MR3)
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{
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int regno = slot->opnd[i].X_add_number - REG_GR;
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/* Ignore invalid operands; they generate errors elsewhere. */
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if (regno >= 128)
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return 0;
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if (idesc->operands[i] == IA64_OPND_R3)
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{
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if (strcmp (idesc->name, "fc") != 0
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&& strcmp (idesc->name, "tak") != 0
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&& strcmp (idesc->name, "thash") != 0
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&& strcmp (idesc->name, "tpa") != 0
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&& strcmp (idesc->name, "ttag") != 0
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&& strncmp (idesc->name, "ptr", 3) != 0
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&& strncmp (idesc->name, "ptc", 3) != 0
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&& strncmp (idesc->name, "probe", 5) != 0)
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return 0;
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}
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if (prev_group->g_reg_set_conditionally[regno])
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return 1;
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}
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}
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return 0;
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}
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static void
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build_insn (slot, insnp)
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struct slot *slot;
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@ -6679,9 +6567,6 @@ emit_one_bundle ()
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dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
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}
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if (errata_nop_necessary_p (md.slot + curr, insn_unit))
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as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
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build_insn (md.slot + curr, insn + i);
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ptr = md.slot[curr].unwind_record;
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@ -6733,12 +6618,6 @@ emit_one_bundle ()
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end_of_insn_group = md.slot[curr].end_of_insn_group;
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if (end_of_insn_group)
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{
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md.group_idx = (md.group_idx + 1) % 3;
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memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
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}
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/* clear slot: */
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ia64_free_opcode (md.slot[curr].idesc);
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memset (md.slot + curr, 0, sizeof (md.slot[curr]));
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