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https://github.com/darlinghq/darling-gdb.git
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Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
* gencode.c (process_instructions): Ensure FP ABS instruction recognised. * interp.c (AbsoluteValue): Add routine. Also provide simple PMON system call support.
This commit is contained in:
Jackie Smith Cashion
parent
69159fad82
commit
a9f7253f64
@ -399,7 +399,7 @@ typedef struct instruction {
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struct instruction MIPS_DECODE[] = {
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/* The instructions are alphabetical, and not in instruction bit-order: */
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{"ABS", 1,"01000110mmm00000dddddaaaaa000101",COP1, FPABS, (FP)},
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{"ABS", 1,"01000110mmm00000vvvvvrrrrr000101",COP1, FPABS, (FP)},
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{"ADD", 1,"000000sssssgggggddddd00000100000",SPECIAL,ADD, (WORD | WORD32 | OVERFLOW)}, /* rd = rs + rt */
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{"ADD", 1,"01000110mmmkkkkkvvvvvrrrrr000000",COP1, FPADD, (FP)},
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{"ADDI", 1,"001000ssssstttttiiiiiiiiiiiiiiii",NORMAL, ADD, (WORD | WORD32 | OVERFLOW)},
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@ -835,7 +835,7 @@ process_instructions(doarch,features)
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printf("switch (num)\n") ;
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printf("{\n");
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for (loop = 1; (loop < limit); loop++) {
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for (loop = 0; (loop < limit); loop++) {
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/* First check that the ISA number we are constructing for is
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valid, before checking if the instruction matches any of the
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architecture specific flags. NOTE: We allow a selected ISA of
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@ -382,6 +382,7 @@ int LOACCESS = 0;
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access to the pipeline cycle count information from the simulator
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engine. */
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unsigned int instruction_fetches = 0;
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unsigned int instruction_fetch_overflow = 0;
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unsigned int pipeline_ticks = 0;
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#endif
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@ -417,9 +418,14 @@ unsigned int rcexit = 0; /* _exit() reason code holder */
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state |= simSKIPNEXT;\
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}
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#define K0BASE (0x80000000)
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#define K0SIZE (0x20000000)
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#define K1BASE (0xA0000000)
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#define K1SIZE (0x20000000)
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/* Very simple memory model to start with: */
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unsigned char *membank = NULL;
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ut_reg membank_base = 0xA0000000;
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ut_reg membank_base = K1BASE;
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unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */
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/* Simple run-time monitor support */
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@ -490,12 +496,18 @@ sim_open (args)
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trust the explicit manifests held in the source: */
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{
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unsigned int s[2];
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s[0] = 0x40805A5A;
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s[1] = 0x00000000;
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if (((float)4.01102924346923828125 != *(float *)s) || ((double)523.2939453125 != *(double *)s)) {
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s[state & simHOSTBE ? 0 : 1] = 0x40805A5A;
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s[state & simHOSTBE ? 1 : 0] = 0x00000000;
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/* TODO: We need to cope with the simulated target and the host
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not having the same endianness. This will require the high and
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low words of a (double) to be swapped when converting between
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the host and the simulated target. */
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if (((float)4.01102924346923828125 != *(float *)(s + ((state & simHOSTBE) ? 0 : 1))) || ((double)523.2939453125 != *(double *)s)) {
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fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
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fprintf(stderr,"*(float *)s = %f (4.01102924346923828125)\n",*(float *)s);
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fprintf(stderr,"*(double *)s = %f (523.2939453125)\n",*(double *)s);
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fprintf(stderr,"*(float *)s = %.20f (4.01102924346923828125)\n",*(float *)s);
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fprintf(stderr,"*(double *)s = %.20f (523.2939453125)\n",*(double *)s);
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exit(1);
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}
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}
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@ -677,7 +689,6 @@ Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
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fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size);
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} else {
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int loop;
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/* TODO: Provide support for PMON monitor */
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/* Entry into the IDT monitor is via fixed address vectors, and
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not using machine instructions. To avoid clashing with use of
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the MIPS TRAP system, we place our own (simulator specific)
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@ -689,6 +700,50 @@ Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
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StoreMemory(cca,AccessLength_WORD,(RSVD_INSTRUCTION | ((loop >> 2) & RSVD_INSTRUCTION_AMASK)),paddr,vaddr,isRAW);
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}
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/* The PMON monitor uses the same address space, but rather than
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branching into it the address of a routine is loaded. We can
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cheat for the moment, and direct the PMON routine to IDT style
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instructions within the monitor space. This relies on the IDT
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monitor not using the locations from 0xBFC00500 onwards as its
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entry points.*/
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for (loop = 0; (loop < 24); loop++)
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{
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uword64 vaddr = (monitor_base + 0x500 + (loop * 4));
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uword64 paddr;
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int cca;
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unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
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switch (loop)
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{
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case 0: /* read */
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value = 7;
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break;
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case 1: /* write */
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value = 8;
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break;
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case 2: /* open */
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value = 6;
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break;
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case 3: /* close */
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value = 10;
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break;
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case 5: /* printf */
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value = ((0x500 - 16) / 8); /* not an IDT reason code */
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break;
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case 8: /* cliexit */
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value = 17;
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break;
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}
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value = (monitor_base + (value * 8));
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
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StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
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else
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callback->printf_filtered(callback,"Failed to write to monitor space 0x%08X%08X\n",WORD64HI(vaddr),WORD64LO(vaddr));
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}
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}
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#if defined(TRACE)
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@ -1110,7 +1165,10 @@ sim_info (verbose)
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callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base));
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#if !defined(FASTSIM)
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callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches);
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if (instruction_fetch_overflow != 0)
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callback->printf_filtered(callback,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow,instruction_fetches);
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else
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callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches);
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callback->printf_filtered(callback,"Pipeline ticks = %d\n",pipeline_ticks);
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/* It would be a useful feature, if when performing multi-cycle
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simulations (rather than single-stepping) we keep the start and
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@ -1394,7 +1452,7 @@ sim_trace()
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/*-- Private simulator support interface ------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Simple monitor interface (currently setup for the IDT monitor) */
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/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
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static void
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sim_monitor(reason)
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unsigned int reason;
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@ -1513,6 +1571,22 @@ sim_monitor(reason)
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}
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break;
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case 158 : /* PMON printf */
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/* in: A0 = pointer to format string */
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/* A1 = optional argument 1 */
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/* A2 = optional argument 2 */
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/* A3 = optional argument 3 */
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/* out: void */
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{
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uword64 paddr;
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int cca;
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if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
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callback->printf_filtered(callback,(char *)((int)paddr),(int)A1,(int)A2,(int)A2);
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else
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callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
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}
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break;
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default:
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callback->printf_filtered(callback,"TODO: sim_monitor(%d) : PC = 0x%08X%08X\n",reason,WORD64HI(IPC),WORD64LO(IPC));
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callback->printf_filtered(callback,"(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)\n",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3));
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@ -1730,6 +1804,19 @@ AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw)
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/* For a simple (flat) memory model, we simply pass virtual
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addressess through (mostly) unchanged. */
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vAddr &= 0xFFFFFFFF;
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/* Treat the kernel memory spaces identically for the moment: */
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if ((membank_base == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE)))
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vAddr += (K1BASE - K0BASE);
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/* Also assume that the K1BASE memory wraps. This is required to
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allow the PMON run-time __sizemem() routine to function (without
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having to provide exception simulation). NOTE: A kludge to work
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around the fact that the monitor memory is currently held in the
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K1BASE space. */
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if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE)))
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vAddr = (K1BASE | (vAddr & (membank_size - 1)));
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*pAddr = vAddr; /* default for isTARGET */
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*CCA = Uncached; /* not used for isHOST */
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@ -1744,7 +1831,7 @@ AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw)
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*pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))];
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} else {
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#if 1 /* def DEBUG */
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callback->printf_filtered(callback,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"));
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callback->printf_filtered(callback,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),WORD64HI(IPC),WORD64LO(IPC));
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#endif /* DEBUG */
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res = 0; /* AddressTranslation has failed */
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*pAddr = -1;
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@ -2189,10 +2276,15 @@ CacheOp(op,pAddr,vAddr,instruction)
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uword64 vAddr;
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unsigned int instruction;
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{
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static int icache_warning = 0;
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static int dcache_warning = 0;
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/* If CP0 is not useable (User or Supervisor mode) and the CP0
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enable bit in the Status Register is clear - a coprocessor
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unusable exception is taken. */
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#if 0
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callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
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#endif
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switch (op & 0x3) {
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case 0: /* instruction cache */
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@ -2203,7 +2295,11 @@ CacheOp(op,pAddr,vAddr,instruction)
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case 4: /* Hit Invalidate */
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case 5: /* Fill */
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case 6: /* Hit Writeback */
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callback->printf_filtered(callback,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op >> 2));
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if (!icache_warning)
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{
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callback->printf_filtered(callback,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op >> 2));
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icache_warning = 1;
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}
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break;
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default:
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@ -2221,7 +2317,11 @@ CacheOp(op,pAddr,vAddr,instruction)
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case 4: /* Hit Invalidate */
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case 5: /* Hit Writeback Invalidate */
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case 6: /* Hit Writeback */
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callback->printf_filtered(callback,"SIM Warning: Data CACHE operation %d to be coded\n",(op >> 2));
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if (!dcache_warning)
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{
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callback->printf_filtered(callback,"SIM Warning: Data CACHE operation %d to be coded\n",(op >> 2));
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dcache_warning = 1;
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}
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break;
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default:
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@ -2611,6 +2711,36 @@ Equal(op1,op2,fmt)
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return(boolean);
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}
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static uword64
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AbsoluteValue(op,fmt)
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uword64 op;
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FP_formats fmt;
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{
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uword64 result;
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#ifdef DEBUG
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printf("DBG: AbsoluteValue: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
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#endif /* DEBUG */
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/* The format type should already have been checked: */
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switch (fmt) {
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case fmt_single:
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{
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unsigned int wop = (unsigned int)op;
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float tmp = ((float)fabs((double)*(float *)&wop));
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result = (uword64)*(unsigned int *)&tmp;
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}
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break;
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case fmt_double:
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{
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double tmp = (fabs(*(double *)&op));
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result = *(uword64 *)&tmp;
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}
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}
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return(result);
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}
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static uword64
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Negate(op,fmt)
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uword64 op;
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@ -2691,7 +2821,7 @@ Sub(op1,op2,fmt)
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uword64 result;
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#ifdef DEBUG
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printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64H(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
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printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
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#endif /* DEBUG */
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/* The registers must specify FPRs valid for operands of type
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@ -3311,8 +3441,15 @@ simulate ()
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callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction,WORD64HI(PC),WORD64LO(PC));
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#endif /* DEBUG */
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/*DBG*/ if (instruction == 0x46200005) /* ABS.D */
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/*DBG*/ callback->printf_filtered(callback,"DBG: ABS.D (0x%08X) instruction\n",instruction);
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#if !defined(FASTSIM) || defined(PROFILE)
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instruction_fetches++;
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/* Since we increment above, the value should only ever be zero if
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we have just overflowed: */
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if (instruction_fetches == 0)
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instruction_fetch_overflow++;
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#if defined(PROFILE)
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if ((state & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) {
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int n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2));
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