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gas/
* config/bfin-parse.y: Remove trailing whitespace. (ccstat): Indent. * config/tc-bfin.c (struct bfin_reg_entry): Remove. (bfin_reg_info[]): Remove. opcodes/ * bfin-dis.c (_print_insn_bfin): Don't declare. (print_insn_bfin): Don't declare. (dregs_pair): Remove. (ignore_bits): Remove. (ccstat): Remove.
This commit is contained in:
Jie Zhang
parent
f31bf2c696
commit
ad15c38ee6
@ -1,3 +1,10 @@
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* config/bfin-parse.y: Remove trailing whitespace.
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(ccstat): Indent.
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* config/tc-bfin.c (struct bfin_reg_entry): Remove.
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(bfin_reg_info[]): Remove.
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* config/bfin-defs.h (F_REG_ALL): Remove macro.
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@ -546,7 +546,7 @@ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
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%type <reg> a_minusassign
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%type <macfunc> multiply_halfregs
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%type <macfunc> assign_macfunc
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%type <macfunc> a_macfunc
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%type <macfunc> a_macfunc
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%type <expr> expr_1
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%type <instr> asm_1
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%type <r0> vmod
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@ -4248,27 +4248,27 @@ cc_op:
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ccstat:
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CCREG cc_op STATUS_REG
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{
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$$.r0 = $3.regno;
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$$.x0 = $2.r0;
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$$.s0 = 0;
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$$.r0 = $3.regno;
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$$.x0 = $2.r0;
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$$.s0 = 0;
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}
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| CCREG cc_op V
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{
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$$.r0 = 0x18;
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$$.x0 = $2.r0;
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$$.s0 = 0;
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$$.r0 = 0x18;
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$$.x0 = $2.r0;
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$$.s0 = 0;
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}
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| STATUS_REG cc_op CCREG
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{
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$$.r0 = $1.regno;
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$$.x0 = $2.r0;
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$$.s0 = 1;
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$$.r0 = $1.regno;
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$$.x0 = $2.r0;
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$$.s0 = 1;
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}
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| V cc_op CCREG
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{
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$$.r0 = 0x18;
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$$.x0 = $2.r0;
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$$.s0 = 1;
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$$.r0 = 0x18;
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$$.x0 = $2.r0;
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$$.s0 = 1;
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}
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;
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@ -57,163 +57,6 @@ FILE *errorf;
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static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
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static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0;
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/* Registers list. */
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struct bfin_reg_entry
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{
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const char *name;
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int number;
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};
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static const struct bfin_reg_entry bfin_reg_info[] = {
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{"R0.L", REG_RL0},
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{"R1.L", REG_RL1},
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{"R2.L", REG_RL2},
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{"R3.L", REG_RL3},
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{"R4.L", REG_RL4},
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{"R5.L", REG_RL5},
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{"R6.L", REG_RL6},
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{"R7.L", REG_RL7},
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{"R0.H", REG_RH0},
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{"R1.H", REG_RH1},
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{"R2.H", REG_RH2},
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{"R3.H", REG_RH3},
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{"R4.H", REG_RH4},
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{"R5.H", REG_RH5},
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{"R6.H", REG_RH6},
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{"R7.H", REG_RH7},
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{"R0", REG_R0},
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{"R1", REG_R1},
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{"R2", REG_R2},
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{"R3", REG_R3},
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{"R4", REG_R4},
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{"R5", REG_R5},
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{"R6", REG_R6},
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{"R7", REG_R7},
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{"P0", REG_P0},
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{"P0.H", REG_P0},
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{"P0.L", REG_P0},
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{"P1", REG_P1},
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{"P1.H", REG_P1},
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{"P1.L", REG_P1},
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{"P2", REG_P2},
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{"P2.H", REG_P2},
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{"P2.L", REG_P2},
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{"P3", REG_P3},
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{"P3.H", REG_P3},
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{"P3.L", REG_P3},
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{"P4", REG_P4},
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{"P4.H", REG_P4},
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{"P4.L", REG_P4},
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{"P5", REG_P5},
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{"P5.H", REG_P5},
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{"P5.L", REG_P5},
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{"SP", REG_SP},
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{"SP.L", REG_SP},
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{"SP.H", REG_SP},
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{"FP", REG_FP},
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{"FP.L", REG_FP},
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{"FP.H", REG_FP},
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{"A0x", REG_A0x},
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{"A1x", REG_A1x},
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{"A0w", REG_A0w},
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{"A1w", REG_A1w},
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{"A0.x", REG_A0x},
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{"A1.x", REG_A1x},
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{"A0.w", REG_A0w},
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{"A1.w", REG_A1w},
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{"A0", REG_A0},
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{"A0.L", REG_A0},
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{"A0.H", REG_A0},
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{"A1", REG_A1},
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{"A1.L", REG_A1},
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{"A1.H", REG_A1},
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{"I0", REG_I0},
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{"I0.L", REG_I0},
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{"I0.H", REG_I0},
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{"I1", REG_I1},
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{"I1.L", REG_I1},
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{"I1.H", REG_I1},
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{"I2", REG_I2},
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{"I2.L", REG_I2},
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{"I2.H", REG_I2},
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{"I3", REG_I3},
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{"I3.L", REG_I3},
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{"I3.H", REG_I3},
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{"M0", REG_M0},
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{"M0.H", REG_M0},
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{"M0.L", REG_M0},
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{"M1", REG_M1},
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{"M1.H", REG_M1},
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{"M1.L", REG_M1},
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{"M2", REG_M2},
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{"M2.H", REG_M2},
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{"M2.L", REG_M2},
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{"M3", REG_M3},
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{"M3.H", REG_M3},
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{"M3.L", REG_M3},
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{"B0", REG_B0},
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{"B0.H", REG_B0},
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{"B0.L", REG_B0},
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{"B1", REG_B1},
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{"B1.H", REG_B1},
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{"B1.L", REG_B1},
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{"B2", REG_B2},
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{"B2.H", REG_B2},
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{"B2.L", REG_B2},
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{"B3", REG_B3},
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{"B3.H", REG_B3},
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{"B3.L", REG_B3},
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{"L0", REG_L0},
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{"L0.H", REG_L0},
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{"L0.L", REG_L0},
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{"L1", REG_L1},
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{"L1.H", REG_L1},
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{"L1.L", REG_L1},
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{"L2", REG_L2},
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{"L2.H", REG_L2},
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{"L2.L", REG_L2},
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{"L3", REG_L3},
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{"L3.H", REG_L3},
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{"L3.L", REG_L3},
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{"AZ", S_AZ},
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{"AN", S_AN},
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{"AC0", S_AC0},
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{"AC1", S_AC1},
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{"AV0", S_AV0},
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{"AV0S", S_AV0S},
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{"AV1", S_AV1},
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{"AV1S", S_AV1S},
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{"AQ", S_AQ},
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{"V", S_V},
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{"VS", S_VS},
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{"sftreset", REG_sftreset},
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{"omode", REG_omode},
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{"excause", REG_excause},
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{"emucause", REG_emucause},
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{"idle_req", REG_idle_req},
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{"hwerrcause", REG_hwerrcause},
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{"CC", REG_CC},
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{"LC0", REG_LC0},
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{"LC1", REG_LC1},
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{"ASTAT", REG_ASTAT},
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{"RETS", REG_RETS},
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{"LT0", REG_LT0},
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{"LB0", REG_LB0},
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{"LT1", REG_LT1},
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{"LB1", REG_LB1},
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{"CYCLES", REG_CYCLES},
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{"CYCLES2", REG_CYCLES2},
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{"USP", REG_USP},
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{"SEQSTAT", REG_SEQSTAT},
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{"SYSCFG", REG_SYSCFG},
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{"RETI", REG_RETI},
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{"RETX", REG_RETX},
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{"RETN", REG_RETN},
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{"RETE", REG_RETE},
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{"EMUDAT", REG_EMUDAT},
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{0, 0}
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};
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/* Blackfin specific function to handle FD-PIC pointer initializations. */
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static void
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@ -1,3 +1,11 @@
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* bfin-dis.c (_print_insn_bfin): Don't declare.
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(print_insn_bfin): Don't declare.
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(dregs_pair): Remove.
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(ignore_bits): Remove.
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(ccstat): Remove.
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2009-09-03 Jie Zhang <jie.zhang@analog.com>
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* bfin-dis.c (IS_DREG): Define.
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@ -123,9 +123,6 @@ static struct
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{ "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
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};
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int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
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int print_insn_bfin (bfd_vma pc, disassemble_info * outf);
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static char comment = 0;
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static char parallel = 0;
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@ -317,7 +314,6 @@ static enum machine_registers decode_dregs_byte[] =
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};
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#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
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#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
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/* P(0..5) SP FP. */
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static enum machine_registers decode_pregs[] =
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@ -408,9 +404,7 @@ static enum machine_registers decode_statbits[] =
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REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
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};
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#define statbits(x) REGNAME (decode_statbits[(x) & 31])
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#define ignore_bits(x) REGNAME (decode_ignore_bits[(x) & 7])
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#define ccstat(x) REGNAME (decode_ccstat[(x) & 0])
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#define statbits(x) REGNAME (decode_statbits[(x) & 31])
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/* LC0 LC1. */
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static enum machine_registers decode_counters[] =
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@ -4624,7 +4618,7 @@ decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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return 4;
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}
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int
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static int
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_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
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{
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bfd_byte buf[4];
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