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* config/tc-mips.c (macro): Don't use the target register as a
base register when building the address for M_L{W,D}{L,R}_AB.
This commit is contained in:
Ian Lance Taylor
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@ -1,5 +1,13 @@
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Wed Feb 15 11:46:02 1995 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-mips.c (macro): Don't use the target register as a
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base register when building the address for M_L{W,D}{L,R}_AB.
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Mon Feb 13 14:44:32 1995 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-mips.c (KT0, KT1): Define.
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(mips_ip): Recognize $kt0 and $kt1 as register names.
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* config/tc-sparc.h (tc_fix_adjustable): Define if OBJ_ELF.
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* config/tc-sparc.c (md_apply_fix): If OBJ_ELF, subtract out the
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value of a defined symbol; the value was added in by
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@ -24,6 +24,7 @@
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#include "as.h"
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#include "config.h"
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#include "subsegs.h"
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#include "libiberty.h"
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#include <ctype.h>
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@ -51,6 +52,8 @@ static char *mips_regmask_frag;
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#define AT 1
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#define PIC_CALL_REG 25
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#define KT0 26
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#define KT1 27
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#define GP 28
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#define SP 29
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#define FP 30
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@ -118,6 +121,9 @@ static int file_mips_isa;
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/* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
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static int mips_cpu = -1;
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/* Whether the 4650 instructions (mad/madu) are permitted. */
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static int mips_4650 = -1;
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/* MIPS PIC level. */
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enum mips_pic_level
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@ -561,6 +567,14 @@ md_begin ()
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if (mips_cpu == -1)
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mips_cpu = 4600;
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}
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else if (strcmp (cpu, "r4650") == 0)
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{
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mips_isa = 3;
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if (mips_cpu == -1)
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mips_cpu = 4650;
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if (mips_4650 == -1)
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mips_4650 = 1;
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}
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else
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{
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mips_isa = 1;
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@ -572,6 +586,9 @@ md_begin ()
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free (a);
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}
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if (mips_4650 < 0)
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mips_4650 = 0;
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if (mips_isa < 2 && mips_trap)
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as_bad ("trap exception not supported at ISA 1");
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@ -892,18 +909,20 @@ append_insn (place, ip, address_expr, reloc_type)
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{
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/* The previous instruction reads the LO register; if the
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current instruction writes to the LO register, we must
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insert two NOPS. */
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if (mips_optimize == 0
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|| (pinfo & INSN_WRITE_LO))
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insert two NOPS. The R4650 has interlocks. */
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if (! mips_4650
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_LO)))
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nops += 2;
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}
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else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
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{
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/* The previous instruction reads the HI register; if the
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current instruction writes to the HI register, we must
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insert a NOP. */
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if (mips_optimize == 0
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|| (pinfo & INSN_WRITE_HI))
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insert a NOP. The R4650 has interlocks. */
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if (! mips_4650
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_HI)))
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nops += 2;
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}
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@ -911,18 +930,20 @@ append_insn (place, ip, address_expr, reloc_type)
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instructions: 1) setting the condition codes using a move to
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coprocessor instruction which requires a general coprocessor
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delay and then reading the condition codes 2) reading the HI
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or LO register and then writing to it. If we are not already
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emitting a NOP instruction, we must check for these cases
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compared to the instruction previous to the previous
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instruction. */
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or LO register and then writing to it (except on the R4650,
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which has interlocks). If we are not already emitting a NOP
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instruction, we must check for these cases compared to the
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instruction previous to the previous instruction. */
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if (nops == 0
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&& (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
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&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
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&& (pinfo & INSN_READ_COND_CODE))
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
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&& (pinfo & INSN_WRITE_LO))
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&& (pinfo & INSN_WRITE_LO)
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&& ! mips_4650)
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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&& (pinfo & INSN_WRITE_HI))))
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&& (pinfo & INSN_WRITE_HI)
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&& ! mips_4650)))
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++nops;
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/* If we are being given a nop instruction, don't bother with
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@ -1079,9 +1100,11 @@ append_insn (place, ip, address_expr, reloc_type)
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|| (prev_pinfo
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& (INSN_LOAD_COPROC_DELAY
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| INSN_COPROC_MOVE_DELAY
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| INSN_WRITE_COND_CODE
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| INSN_READ_LO
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| INSN_READ_HI))
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| INSN_WRITE_COND_CODE))
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|| (! mips_4650
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&& (prev_pinfo
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& (INSN_READ_LO
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| INSN_READ_HI)))
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|| (mips_isa < 2
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&& (prev_pinfo
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& (INSN_LOAD_MEMORY_DELAY
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@ -1265,9 +1288,11 @@ mips_emit_delays ()
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if ((prev_insn.insn_mo->pinfo
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& (INSN_LOAD_COPROC_DELAY
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| INSN_COPROC_MOVE_DELAY
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| INSN_WRITE_COND_CODE
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| INSN_READ_LO
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| INSN_READ_HI))
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| INSN_WRITE_COND_CODE))
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|| (! mips_4650
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&& (prev_insn.insn_mo->pinfo
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& (INSN_READ_LO
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| INSN_READ_HI)))
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|| (mips_isa < 2
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&& (prev_insn.insn_mo->pinfo
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& (INSN_LOAD_MEMORY_DELAY
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@ -1275,13 +1300,15 @@ mips_emit_delays ()
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{
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nop = 1;
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if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
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|| (prev_insn.insn_mo->pinfo & INSN_READ_HI)
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|| (prev_insn.insn_mo->pinfo & INSN_READ_LO))
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|| (! mips_4650
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&& ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
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|| (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
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emit_nop ();
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}
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else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
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|| (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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|| (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))
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|| (! mips_4650
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&& ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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|| (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
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nop = 1;
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if (nop)
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{
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@ -1814,6 +1841,7 @@ macro (ip)
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int likely = 0;
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int dbl = 0;
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int coproc = 0;
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int lr = 0;
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offsetT maxnum;
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bfd_reloc_code_real_type r;
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char *p;
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@ -2821,9 +2849,11 @@ macro (ip)
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goto ld;
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case M_LWL_AB:
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s = "lwl";
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lr = 1;
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goto ld;
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case M_LWR_AB:
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s = "lwr";
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lr = 1;
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goto ld;
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case M_LDC1_AB:
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s = "ldc1";
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@ -2839,9 +2869,11 @@ macro (ip)
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goto ld;
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case M_LDL_AB:
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s = "ldl";
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lr = 1;
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goto ld;
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case M_LDR_AB:
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s = "ldr";
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lr = 1;
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goto ld;
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case M_LL_AB:
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s = "ll";
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@ -2852,7 +2884,7 @@ macro (ip)
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case M_LWU_AB:
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s = "lwu";
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ld:
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if (breg == treg || coproc)
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if (breg == treg || coproc || lr)
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{
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tempreg = AT;
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used_at = 1;
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@ -4186,14 +4218,16 @@ mips_ip (str, ip)
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if (insn->pinfo == INSN_MACRO)
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insn_isa = insn->match;
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else if (insn->pinfo & INSN_ISA2)
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else if ((insn->pinfo & INSN_ISA) == INSN_ISA2)
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insn_isa = 2;
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else if (insn->pinfo & INSN_ISA3)
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else if ((insn->pinfo & INSN_ISA) == INSN_ISA3)
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insn_isa = 3;
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else
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insn_isa = 1;
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if (insn_isa > mips_isa)
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if (insn_isa > mips_isa
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|| ((insn->pinfo & INSN_ISA) == INSN_4650
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&& ! mips_4650))
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{
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if (insn + 1 < &mips_opcodes[NUMOPCODES]
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&& strcmp (insn->name, insn[1].name) == 0)
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@ -4387,6 +4421,16 @@ mips_ip (str, ip)
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s += 3;
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regno = AT;
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}
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else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
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{
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s += 4;
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regno = KT0;
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}
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else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
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{
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s += 4;
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regno = KT1;
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}
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else
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goto notreg;
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}
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@ -5035,6 +5079,10 @@ struct option md_longopts[] = {
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{"EB", no_argument, NULL, OPTION_EB},
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#define OPTION_EL (OPTION_MD_BASE + 11)
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{"EL", no_argument, NULL, OPTION_EL},
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#define OPTION_M4650 (OPTION_MD_BASE + 12)
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{"m4650", no_argument, NULL, OPTION_M4650},
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#define OPTION_NO_M4650 (OPTION_MD_BASE + 13)
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{"no-m4650", no_argument, NULL, OPTION_NO_M4650},
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#ifdef OBJ_ELF
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#define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
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@ -5159,6 +5207,12 @@ md_parse_option (c, arg)
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mips_cpu = 4400;
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else if (strcmp (p, "4600") == 0)
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mips_cpu = 4600;
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else if (strcmp (p, "4650") == 0)
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{
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mips_cpu = 4650;
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if (mips_4650 < 0)
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mips_4650 = 1;
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}
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break;
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case '6':
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@ -5183,6 +5237,14 @@ md_parse_option (c, arg)
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}
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break;
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case OPTION_M4650:
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mips_4650 = 1;
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break;
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case OPTION_NO_M4650:
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mips_4650 = 0;
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break;
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case OPTION_MEMBEDDED_PIC:
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mips_pic = EMBEDDED_PIC;
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#ifdef GPOPT
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