darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2025-01-27 12:01:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

* simops.c: Call abort for any instruction that's not currently

Browse Source 
simulated.
This commit is contained in:
Jeff Law 1996-12-06 21:49:27 +00:00
parent 9f4a551e11
commit b2f7a7e5b3
2 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
sim/mn10300/ChangeLog
View File

@ -1,5 +1,8 @@
Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Call abort for any instruction that's not currently
simulated.
* simops.c: Define accessor macros to extract register
values from instructions. Use them consistently.

13
sim/mn10300/simops.c
View File

@ -2976,76 +2976,89 @@ void OP_CB (insn, extension)
void OP_F500 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* getx */
void OP_F6F0 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulq */
void OP_F600 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulq */
void OP_F90000 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulq */
void OP_FB000000 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulq */
void OP_FD000000 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulqu */
void OP_F610 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulqu */
void OP_F91400 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulqu */
void OP_FB140000 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* mulqu */
void OP_FD140000 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* sat16 */
void OP_F640 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* sat24 */
void OP_F650 (insn, extension)
unsigned long insn, extension;
{
abort ()
}
/* bsch */
void OP_F670 (insn, extension)
unsigned long insn, extension;
{
abort ()
}