mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-02-03 23:56:39 +00:00
Tue Aug 20 14:10:02 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* tc-d10v.c: All references to defined symbols should now use the optimal instruction. .float and .double now work.
This commit is contained in:
Martin Hunt
parent
ab457c4c0b
commit
bb5638c637
@ -29,17 +29,19 @@
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const char comment_chars[] = "#;";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char *md_shortopts = "";
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const char *md_shortopts = "O";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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int Optimizing = 0;
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/* fixups */
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#define MAX_INSN_FIXUPS (5)
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struct d10v_fixup
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{
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expressionS exp;
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bfd_reloc_code_real_type reloc;
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int operand;
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int pcrel;
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};
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typedef struct _fixups
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@ -59,6 +61,7 @@ static int check_range PARAMS ((unsigned long num, int bits, int flags));
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static int postfix PARAMS ((char *p));
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static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
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static int get_operands PARAMS ((expressionS exp[]));
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static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
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static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
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static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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@ -67,6 +70,8 @@ static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long ins
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static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
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static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
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offsetT value, int left));
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static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
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struct d10v_opcode *opcode2, unsigned long insn2));
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struct option md_longopts[] = {
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@ -192,7 +197,7 @@ md_show_usage (stream)
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FILE *stream;
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{
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fprintf(stream, "D10V options:\n\
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none yet\n");
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-O optimize. Will do some operations in parallel.\n");
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}
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int
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@ -200,7 +205,16 @@ md_parse_option (c, arg)
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int c;
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char *arg;
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{
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return 0;
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switch (c)
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{
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case 'O':
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/* Optimize. Will attempt to parallelize operations */
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Optimizing = 1;
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break;
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default:
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return 0;
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}
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return 1;
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}
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symbolS *
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@ -210,13 +224,46 @@ md_undefined_symbol (name)
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return 0;
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}
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/* Turn a string in input_line_pointer into a floating point constant of type
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type, and store the appropriate bytes in *litP. The number of LITTLENUMS
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emitted is stored in *sizeP . An error message is returned, or NULL on OK.
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*/
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char *
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md_atof (type, litp, sizep)
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int type;
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char *litp;
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int *sizep;
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md_atof (type, litP, sizeP)
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int type;
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char *litP;
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int *sizeP;
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{
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return "";
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int prec;
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LITTLENUM_TYPE words[4];
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char *t;
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int i;
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switch (type)
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{
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case 'f':
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prec = 2;
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break;
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case 'd':
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prec = 4;
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break;
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default:
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*sizeP = 0;
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return "bad call to md_atof";
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}
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t = atof_ieee (input_line_pointer, type, words);
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if (t)
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input_line_pointer = t;
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*sizeP = prec * 2;
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for (i = 0; i < prec; i++)
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{
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md_number_to_chars (litP, (valueT) words[i], 2);
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litP += 2;
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}
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return NULL;
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}
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void
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@ -466,16 +513,14 @@ build_insn (opcode, opers, insn)
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/*
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printf("need a fixup: ");
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print_expr_1(stdout,&opers[i]);
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printf("\n");ddd
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printf("\n");
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*/
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if (fixups->fc >= MAX_INSN_FIXUPS)
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as_fatal ("too many fixups");
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fixups->fix[fixups->fc].exp = opers[i];
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/* put the operand number here for now. We can look up
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the reloc type and/or fixup the instruction in md_apply_fix() */
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fixups->fix[fixups->fc].reloc = opcode->operands[i];
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fixups->fix[fixups->fc].operand = opcode->operands[i];
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fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
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(fixups->fc)++;
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}
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@ -511,7 +556,7 @@ write_long (opcode, insn, fx)
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for (i=0; i < fx->fc; i++)
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{
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if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]))
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if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].operand]))
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{
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/*
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printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
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@ -523,8 +568,8 @@ write_long (opcode, insn, fx)
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f - frag_now->fr_literal,
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4,
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&(fx->fix[i].exp),
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1,
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fx->fix[i].reloc|2048);
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fx->fix[i].pcrel,
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fx->fix[i].operand|2048);
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}
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}
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fx->fc = 0;
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@ -541,7 +586,7 @@ write_1_short (opcode, insn, fx)
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char *f = frag_more(4);
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int i;
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if (opcode->exec_type == PARONLY)
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if (opcode->exec_type & PARONLY)
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as_fatal ("Instruction must be executed in parallel with another instruction.");
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/* the other container needs to be NOP */
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@ -557,7 +602,7 @@ write_1_short (opcode, insn, fx)
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for (i=0; i < fx->fc; i++)
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{
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bfd_reloc_code_real_type reloc;
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reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]);
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reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].operand]);
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if (reloc)
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{
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/*
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@ -568,14 +613,14 @@ write_1_short (opcode, insn, fx)
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/* if it's an R reloc, we may have to switch it to L */
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if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
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fx->fix[i].reloc |= 1024;
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fx->fix[i].operand |= 1024;
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fix_new_exp (frag_now,
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f - frag_now->fr_literal,
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4,
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&(fx->fix[i].exp),
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1,
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fx->fix[i].reloc|2048);
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fx->fix[i].pcrel,
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fx->fix[i].operand|2048);
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}
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}
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fx->fc = 0;
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@ -594,14 +639,14 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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char *f;
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int i,j;
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if ( (exec_type != 1) && ((opcode1->exec_type == PARONLY)
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|| (opcode2->exec_type == PARONLY)))
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if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY)
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|| (opcode2->exec_type & PARONLY)))
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as_fatal("Instruction must be executed in parallel");
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if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
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as_fatal ("Long instructions may not be combined.");
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if(opcode1->exec_type == BRANCH_LINK)
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if(opcode1->exec_type & BRANCH_LINK)
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{
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/* subroutines must be called from 32-bit boundaries */
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/* so the return address will be correct */
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@ -611,20 +656,34 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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switch (exec_type)
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{
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case 0:
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if (opcode1->unit == IU)
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case 0: /* order not specified */
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if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2))
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{
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/* parallel */
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if (opcode1->unit == IU)
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insn = FM00 | (insn2 << 15) | insn1;
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else if (opcode2->unit == MU)
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insn = FM00 | (insn2 << 15) | insn1;
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else
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{
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insn = FM00 | (insn1 << 15) | insn2;
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fx = fx->next;
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}
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}
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else if (opcode1->unit == IU)
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{
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/* reverse sequential */
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insn = FM10 | (insn2 << 15) | insn1;
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}
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else
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{
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/* sequential */
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insn = FM01 | (insn1 << 15) | insn2;
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fx = fx->next;
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}
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break;
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case 1: /* parallel */
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if (opcode1->exec_type == SEQ || opcode2->exec_type == SEQ)
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if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
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as_fatal ("One of these instructions may not be executed in parallel.");
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if (opcode1->unit == IU)
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@ -633,7 +692,6 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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as_fatal ("Two IU instructions may not be executed in parallel");
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as_warn ("Swapping instruction order");
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insn = FM00 | (insn2 << 15) | insn1;
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fx = fx->next;
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}
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else if (opcode2->unit == MU)
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{
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@ -641,11 +699,12 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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as_fatal ("Two MU instructions may not be executed in parallel");
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as_warn ("Swapping instruction order");
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insn = FM00 | (insn2 << 15) | insn1;
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fx = fx->next;
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}
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else
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insn = FM00 | (insn1 << 15) | insn2;
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fx = fx->next;
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{
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insn = FM00 | (insn1 << 15) | insn2;
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fx = fx->next;
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}
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break;
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case 2: /* sequential */
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if (opcode1->unit == IU)
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@ -657,6 +716,7 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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if (opcode2->unit == MU)
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as_fatal ("MU instruction may not be in the right container");
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insn = FM10 | (insn1 << 15) | insn2;
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fx = fx->next;
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break;
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default:
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as_fatal("unknown execution type passed to write_2_short()");
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@ -666,38 +726,132 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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f = frag_more(4);
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number_to_chars_bigendian (f, insn, 4);
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for (j=0; j<2; j++)
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{
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bfd_reloc_code_real_type reloc;
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for (i=0; i < fx->fc; i++)
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{
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reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]);
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if (reloc)
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{
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if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
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fx->fix[i].reloc |= 1024;
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/*
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printf("fix_new_exp: where:%x reloc:%d\n ",f - frag_now->fr_literal,fx->fix[i].reloc);
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print_expr_1(stdout,&(fx->fix[i].exp));
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printf("\n");
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*/
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fix_new_exp (frag_now,
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f - frag_now->fr_literal,
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4,
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&(fx->fix[i].exp),
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1,
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fx->fix[i].reloc|2048);
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}
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}
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fx->fc = 0;
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fx = fx->next;
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}
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for (j=0; j<2; j++)
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{
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bfd_reloc_code_real_type reloc;
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for (i=0; i < fx->fc; i++)
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{
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reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].operand]);
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if (reloc)
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{
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if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
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fx->fix[i].operand |= 1024;
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/*
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printf("fix_new_exp: where:%x reloc:%d\n ",f - frag_now->fr_literal,fx->fix[i].operand);
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print_expr_1(stdout,&(fx->fix[i].exp));
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printf("\n");
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*/
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fix_new_exp (frag_now,
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f - frag_now->fr_literal,
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4,
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&(fx->fix[i].exp),
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fx->fix[i].pcrel,
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fx->fix[i].operand|2048);
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}
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}
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fx->fc = 0;
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fx = fx->next;
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}
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return (0);
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}
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/* Check 2 instructions and determine if they can be safely */
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/* executed in parallel. Returns 1 if they can be. */
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static int
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parallel_ok (op1, insn1, op2, insn2)
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struct d10v_opcode *op1, *op2;
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unsigned long insn1, insn2;
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{
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int i, j, flags, mask, shift, regno;
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unsigned long ins, mod[2], used[2];
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struct d10v_opcode *op;
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if (op1->exec_type & SEQ || op2->exec_type & SEQ)
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return 0;
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/* The idea here is to create two sets of bitmasks (mod and used) */
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/* which indicate which registers are modified or used by each instruction. */
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/* The operation can only be done in parallel if instruction 1 and instruction 2 */
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/* modify different registers, and neither instruction modifies any registers */
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/* the other is using. Accesses to control registers, PSW, and memory are treated */
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/* as accesses to a single register. So if both instructions write memory or one */
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/* instruction writes memory and the other reads, then they cannot be done in parallel. */
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/* Likewise, if one instruction mucks with the psw and the other reads the PSW */
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/* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
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/* the bitmasks (mod and used) look like this (bit 31 = MSB) */
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/* r0-r15 0-15 */
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/* a0-a1 16-17 */
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/* cr (not psw) 18 */
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/* psw 19 */
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/* mem 20 */
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for (j=0;j<2;j++)
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{
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if (j == 0)
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{
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op = op1;
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ins = insn1;
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}
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else
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{
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op = op2;
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ins = insn2;
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}
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mod[j] = used[j] = 0;
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for (i = 0; op1->operands[i]; i++)
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{
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flags = d10v_operands[op->operands[i]].flags;
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shift = d10v_operands[op->operands[i]].shift;
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mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
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if (flags & OPERAND_REG)
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{
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regno = (ins >> shift) & mask;
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if (flags & OPERAND_ACC)
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regno += 16;
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else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
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{
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if (regno == 0)
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regno = 19;
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else
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regno = 18;
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}
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else if (flags & OPERAND_FLAG)
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regno = 19;
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if ( flags & OPERAND_DEST )
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{
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mod[j] |= 1 << regno;
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if (flags & OPERAND_EVEN)
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mod[j] |= 1 << (regno + 1);
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}
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else
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{
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used[j] |= 1 << regno ;
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if (flags & OPERAND_EVEN)
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used[j] |= 1 << (regno + 1);
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}
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}
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else if (op->exec_type & RMEM)
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used[j] |= 1 << 20;
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else if (op->exec_type & WMEM)
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mod[j] |= 1 << 20;
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else if (op->exec_type & RF0)
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used[j] |= 1 << 19;
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else if (op->exec_type & WF0)
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mod[j] |= 1 << 19;
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else if (op->exec_type & WCAR)
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mod[j] |= 1 << 19;
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}
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}
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if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0)
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return 1;
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return 0;
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}
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/* This is the main entry point for the machine-dependent assembler. str points to a
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machine-dependent instruction. This function is supposed to emit the frags/bytes
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it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
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@ -817,11 +971,10 @@ do_assemble (str, opcode)
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||||
char *str;
|
||||
struct d10v_opcode **opcode;
|
||||
{
|
||||
struct d10v_opcode *next_opcode;
|
||||
unsigned char *op_start, *save;
|
||||
unsigned char *op_end;
|
||||
char name[20];
|
||||
int nlen = 0, i, match, numops;
|
||||
int nlen = 0;
|
||||
expressionS myops[6];
|
||||
unsigned long insn;
|
||||
|
||||
@ -853,52 +1006,75 @@ do_assemble (str, opcode)
|
||||
|
||||
save = input_line_pointer;
|
||||
input_line_pointer = op_end;
|
||||
*opcode = find_opcode (*opcode, myops);
|
||||
if (*opcode == 0)
|
||||
return -1;
|
||||
input_line_pointer = save;
|
||||
|
||||
insn = build_insn ((*opcode), myops, 0);
|
||||
/* printf("sub-insn = %lx\n",insn); */
|
||||
return (insn);
|
||||
}
|
||||
|
||||
/* find_opcode() gets a pointer to an entry in the opcode table. */
|
||||
/* It must look at all opcodes with the same name and use the operands */
|
||||
/* to choose the correct opcode. */
|
||||
|
||||
static struct d10v_opcode *
|
||||
find_opcode (opcode, myops)
|
||||
struct d10v_opcode *opcode;
|
||||
expressionS myops[];
|
||||
{
|
||||
int i, match, done, numops;
|
||||
struct d10v_opcode *next_opcode;
|
||||
|
||||
/* get all the operands and save them as expressions */
|
||||
numops = get_operands (myops);
|
||||
|
||||
/* now see if the operand is a fake. If so, find the correct size */
|
||||
/* instruction, if possible */
|
||||
match = 0;
|
||||
if ((*opcode)->format == OPCODE_FAKE)
|
||||
if (opcode->format == OPCODE_FAKE)
|
||||
{
|
||||
int opnum = (*opcode)->operands[0];
|
||||
if (myops[opnum].X_op == O_constant)
|
||||
int opnum = opcode->operands[0];
|
||||
|
||||
if (myops[opnum].X_op == O_register)
|
||||
{
|
||||
next_opcode=(*opcode)+1;
|
||||
for (i=0; (*opcode)->operands[i+1]; i++)
|
||||
myops[opnum].X_op = O_symbol;
|
||||
myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
|
||||
myops[opnum].X_add_number = 0;
|
||||
myops[opnum].X_op_symbol = NULL;
|
||||
}
|
||||
|
||||
if (myops[opnum].X_op == O_constant || S_IS_DEFINED(myops[opnum].X_add_symbol))
|
||||
{
|
||||
next_opcode=opcode+1;
|
||||
for (i=0; opcode->operands[i+1]; i++)
|
||||
{
|
||||
int bits = d10v_operands[next_opcode->operands[opnum]].bits;
|
||||
int flags = d10v_operands[next_opcode->operands[opnum]].flags;
|
||||
if (!check_range (myops[opnum].X_add_number, bits, flags))
|
||||
{
|
||||
match = 1;
|
||||
break;
|
||||
}
|
||||
return next_opcode;
|
||||
next_opcode++;
|
||||
}
|
||||
as_fatal ("value out of range");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* not a constant, so use a long instruction */
|
||||
next_opcode = (*opcode)+2;
|
||||
match = 1;
|
||||
/* not a constant, so use a long instruction */
|
||||
return opcode+2;
|
||||
}
|
||||
if (match)
|
||||
*opcode = next_opcode;
|
||||
else
|
||||
as_fatal ("value out of range");
|
||||
}
|
||||
else
|
||||
{
|
||||
match = 0;
|
||||
/* now search the opcode table table for one with operands */
|
||||
/* that matches what we've got */
|
||||
while (!match)
|
||||
{
|
||||
match = 1;
|
||||
for (i = 0; (*opcode)->operands[i]; i++)
|
||||
for (i = 0; opcode->operands[i]; i++)
|
||||
{
|
||||
int flags = d10v_operands[(*opcode)->operands[i]].flags;
|
||||
int flags = d10v_operands[opcode->operands[i]].flags;
|
||||
int X_op = myops[i].X_op;
|
||||
int num = myops[i].X_add_number;
|
||||
|
||||
@ -928,21 +1104,20 @@ do_assemble (str, opcode)
|
||||
{
|
||||
match=0;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* we're only done if the operands matched AND there
|
||||
/* we're only done if the operands matched so far AND there
|
||||
are no more to check */
|
||||
if (match && myops[i].X_op==0)
|
||||
break;
|
||||
|
||||
next_opcode = (*opcode)+1;
|
||||
next_opcode = opcode+1;
|
||||
if (next_opcode->opcode == 0)
|
||||
break;
|
||||
if (strcmp(next_opcode->name, (*opcode)->name))
|
||||
if (strcmp(next_opcode->name, opcode->name))
|
||||
break;
|
||||
(*opcode) = next_opcode;
|
||||
opcode = next_opcode;
|
||||
}
|
||||
}
|
||||
|
||||
@ -955,14 +1130,14 @@ do_assemble (str, opcode)
|
||||
/* Check that all registers that are required to be even are. */
|
||||
/* Also, if any operands were marked as registers, but were really symbols */
|
||||
/* fix that here. */
|
||||
for (i=0; (*opcode)->operands[i]; i++)
|
||||
for (i=0; opcode->operands[i]; i++)
|
||||
{
|
||||
if ((d10v_operands[(*opcode)->operands[i]].flags & OPERAND_EVEN) &&
|
||||
if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
|
||||
(myops[i].X_add_number & 1))
|
||||
as_fatal("Register number must be EVEN");
|
||||
if (myops[i].X_op == O_register)
|
||||
{
|
||||
if (!(d10v_operands[(*opcode)->operands[i]].flags & OPERAND_REG))
|
||||
if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
|
||||
{
|
||||
myops[i].X_op = O_symbol;
|
||||
myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
|
||||
@ -971,18 +1146,9 @@ do_assemble (str, opcode)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
input_line_pointer = save;
|
||||
|
||||
/* at this point, we have "opcode" pointing to the opcode entry in the
|
||||
d10v opcode table, with myops filled out with the operands. */
|
||||
insn = build_insn ((*opcode), myops, 0);
|
||||
/* printf("sub-insn = %lx\n",insn); */
|
||||
|
||||
return (insn);
|
||||
return opcode;
|
||||
}
|
||||
|
||||
|
||||
/* if while processing a fixup, a reloc really needs to be created */
|
||||
/* then it is done here */
|
||||
|
||||
@ -1021,8 +1187,10 @@ md_pcrel_from_section (fixp, sec)
|
||||
fixS *fixp;
|
||||
segT sec;
|
||||
{
|
||||
if (fixp->fx_addsy != (symbolS *)NULL && !S_IS_DEFINED (fixp->fx_addsy))
|
||||
return 0;
|
||||
/* return fixp->fx_frag->fr_address + fixp->fx_where; */
|
||||
/* printf("pcrel_from_section: %x\n", fixp->fx_frag->fr_address + fixp->fx_where); */
|
||||
return fixp->fx_frag->fr_address + fixp->fx_where;
|
||||
}
|
||||
|
||||
int
|
||||
@ -1086,10 +1254,7 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
case BFD_RELOC_D10V_10_PCREL_L:
|
||||
case BFD_RELOC_D10V_10_PCREL_R:
|
||||
case BFD_RELOC_D10V_18_PCREL:
|
||||
/* instruction addresses are always right-shifted by 2
|
||||
and pc-relative */
|
||||
if (!fixp->fx_pcrel)
|
||||
value -= fixp->fx_where;
|
||||
/* instruction addresses are always right-shifted by 2 */
|
||||
value >>= 2;
|
||||
break;
|
||||
case BFD_RELOC_32:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user