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For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
through an exception may not work correctly. For GDB reads/writes to the control registers, ensure the cpu state is updated correctly.
This commit is contained in:
Andrew Cagney
parent
0a5875fc63
commit
bc6df23d14
@ -1,3 +1,39 @@
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Mon Dec 8 12:58:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* simops.c (OP_5F00): From Martin Hunt <hunt@cygnus.com>. Change
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reserved trap from 0 to 15. Add trap emulation code for 0-14.
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* interp.c (sim_resume): From Martin Hunt <hunt@cygnus.com>. Check
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IBA for SDBT.
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* d10v_sim.h (AE_VECTOR_START, RIE_VECTOR_START,
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SDBT_VECTOR_START, TRAP_VECTOR_START): Define.
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* simops.c (OP_5F00): For "trap", mask out all but SM bit in PSW,
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use move_to_cr.
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(OP_5F00): For "trap", update BPSW with move_to_cr.
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Fri Dec 5 15:31:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* d10v_sim.h (enum): Enumerate CR register names.
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(enum): Enumerate PSW bit values.
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(PSW): Obtain value uing move_from_cr.
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(MOD_S, MOD_E, BPSW): Make r-values.
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(move_from_cr, move_to_cr): Declare functions.
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* interp.c (sim_fetch_register, sim_store_register): Use
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move_from_cr and move_to_cr for CR register transfers.
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* simops.c (move_from_cr, move_to_cr): New functions.
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(OP_5F40): Move BPSW to PSW using move_to_cr and move_from_cr.
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(OP_5600): For "mvtc", use function move_to_cr.
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(OP_5200): For "mvfc", use function move_from_cr.
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Fri Dec 5 13:33:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* simops.c (OP_5600): For "mvtc" MOD_E and MOD_S, ensure that the
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LSbit is zero.
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Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -109,16 +109,48 @@ extern bfd_vma text_start;
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extern bfd_vma text_end;
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extern bfd *prog_bfd;
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#define PC (State.cregs[2])
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#define PSW (State.cregs[0])
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#define BPSW (State.cregs[1])
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#define BPC (State.cregs[3])
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#define RPT_C (State.cregs[7])
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#define RPT_S (State.cregs[8])
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#define RPT_E (State.cregs[9])
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#define MOD_S (State.cregs[10])
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#define MOD_E (State.cregs[11])
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#define IBA (State.cregs[14])
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enum
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{
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PSW_CR = 0,
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BPSW_CR = 1,
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PC_CR = 2,
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BPC_CR = 3,
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RPT_C_CR = 7,
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RPT_S_CR = 8,
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RPT_E_CR = 9,
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MOD_S_CR = 10,
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MOD_E_CR = 11,
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IBA_CR = 14,
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};
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enum
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{
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PSW_SM_BIT = 0x8000,
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PSW_EA_BIT = 0x2000,
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PSW_DB_BIT = 0x1000,
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PSW_DM_BIT = 0x0800,
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PSW_IE_BIT = 0x0400,
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PSW_RP_BIT = 0x0200,
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PSW_MD_BIT = 0x0100,
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PSW_FX_BIT = 0x0080,
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PSW_ST_BIT = 0x0040,
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PSW_F0_BIT = 0x0008,
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PSW_F1_BIT = 0x0004,
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PSW_C_BIT = 0x0001,
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};
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/* See simopsc.:move_to_cr() for registers that can not be read-from
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or assigned-to directly */
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#define PC (State.cregs[PC_CR])
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#define PSW (move_from_cr (PSW_CR))
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#define BPSW (0 + State.cregs[PSW_CR])
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#define BPC (State.cregs[BPC_CR])
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#define RPT_C (State.cregs[RPT_C_CR])
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#define RPT_S (State.cregs[RPT_E_CR])
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#define RPT_E (State.cregs[RPT_E_CR])
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#define MOD_S (0 + State.cregs[MOD_S_CR])
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#define MOD_E (0 + State.cregs[MOD_E_CR])
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#define IBA (State.cregs[IBA_CR])
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#define SIG_D10V_STOP -1
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#define SIG_D10V_EXIT -2
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@ -194,3 +226,11 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data));
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#define SET_DMAP(x) SW(0xff04,x)
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#define JMP(x) { PC = (x); State.pc_changed = 1; }
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#define AE_VECTOR_START 0xffc3
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#define RIE_VECTOR_START 0xffc2
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#define SDBT_VECTOR_START 0xffd5
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#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
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extern void move_to_cr PARAMS ((int cr, reg_t val));
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extern reg_t move_from_cr PARAMS ((int cr));
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@ -43,6 +43,76 @@ enum op_types {
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OP_R2R3
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};
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void
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move_to_cr (int cr, reg_t val)
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{
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switch (cr)
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{
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case PSW_CR:
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State.SM = (val & PSW_SM_BIT) != 0;
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State.EA = (val & PSW_EA_BIT) != 0;
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State.DB = (val & PSW_DB_BIT) != 0;
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State.DM = (val & PSW_DM_BIT) != 0;
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State.IE = (val & PSW_IE_BIT) != 0;
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State.RP = (val & PSW_RP_BIT) != 0;
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State.MD = (val & PSW_MD_BIT) != 0;
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State.FX = (val & PSW_FX_BIT) != 0;
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State.ST = (val & PSW_ST_BIT) != 0;
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State.F0 = (val & PSW_F0_BIT) != 0;
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State.F1 = (val & PSW_F1_BIT) != 0;
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State.C = (val & PSW_C_BIT) != 0;
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if (State.ST && !State.FX)
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{
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(*d10v_callback->printf_filtered)
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(d10v_callback,
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"ERROR at PC 0x%x: ST can only be set when FX is set.\n",
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PC<<2);
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State.exception = SIGILL;
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}
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State.cregs[PSW_CR] = (val & ~0x4032);
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break;
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case BPSW_CR:
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State.cregs[BPSW_CR] = (val & ~0x4032);
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break;
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case MOD_S_CR:
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case MOD_E_CR:
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State.cregs[cr] = (val & ~0x1);
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break;
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default:
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State.cregs[cr] = val;
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break;
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}
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}
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reg_t
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move_from_cr (int cr)
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{
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reg_t val = 0;
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switch (cr)
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{
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case PSW_CR:
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if (State.SM) val |= PSW_SM_BIT;
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if (State.EA) val |= PSW_EA_BIT;
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if (State.DB) val |= PSW_DB_BIT;
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if (State.DM) val |= PSW_DM_BIT;
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if (State.IE) val |= PSW_IE_BIT;
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if (State.RP) val |= PSW_RP_BIT;
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if (State.MD) val |= PSW_MD_BIT;
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if (State.FX) val |= PSW_FX_BIT;
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if (State.ST) val |= PSW_ST_BIT;
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if (State.F0) val |= PSW_F0_BIT;
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if (State.F1) val |= PSW_F1_BIT;
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if (State.C) val |= PSW_C_BIT;
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break;
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default:
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val = State.cregs[cr];
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break;
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}
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return val;
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}
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#ifdef DEBUG
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static void trace_input_func PARAMS ((char *name,
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enum op_types in1,
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@ -1704,24 +1774,7 @@ void
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OP_5200 ()
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{
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trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
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if (OP[1] == 0)
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{
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/* PSW is treated specially */
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PSW = 0;
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if (State.SM) PSW |= 0x8000;
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if (State.EA) PSW |= 0x2000;
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if (State.DB) PSW |= 0x1000;
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if (State.DM) PSW |= 0x800;
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if (State.IE) PSW |= 0x400;
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if (State.RP) PSW |= 0x200;
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if (State.MD) PSW |= 0x100;
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if (State.FX) PSW |= 0x80;
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if (State.ST) PSW |= 0x40;
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if (State.F0) PSW |= 8;
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if (State.F1) PSW |= 4;
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if (State.C) PSW |= 1;
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}
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State.regs[OP[0]] = State.cregs[OP[1]];
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State.regs[OP[0]] = move_from_cr (OP[1]);
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trace_output (OP_REG);
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}
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@ -1761,30 +1814,7 @@ void
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OP_5600 ()
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{
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trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
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State.cregs[OP[1]] = State.regs[OP[0]];
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if (OP[1] == 0)
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{
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/* PSW is treated specially */
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State.SM = (PSW & 0x8000) ? 1 : 0;
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State.EA = (PSW & 0x2000) ? 1 : 0;
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State.DB = (PSW & 0x1000) ? 1 : 0;
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State.DM = (PSW & 0x800) ? 1 : 0;
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State.IE = (PSW & 0x400) ? 1 : 0;
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State.RP = (PSW & 0x200) ? 1 : 0;
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State.MD = (PSW & 0x100) ? 1 : 0;
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State.FX = (PSW & 0x80) ? 1 : 0;
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State.ST = (PSW & 0x40) ? 1 : 0;
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State.F0 = (PSW & 8) ? 1 : 0;
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State.F1 = (PSW & 4) ? 1 : 0;
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State.C = PSW & 1;
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if (State.ST && !State.FX)
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{
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(*d10v_callback->printf_filtered) (d10v_callback,
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"ERROR at PC 0x%x: ST can only be set when FX is set.\n",
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PC<<2);
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State.exception = SIGILL;
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}
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}
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move_to_cr (OP[1], State.regs[OP[0]]);
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trace_output (OP_CR_REVERSE);
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}
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@ -2033,7 +2063,7 @@ OP_5F40 ()
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{
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trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
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PC = BPC;
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PSW = BPSW;
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move_to_cr (PSW_CR, BPSW);
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trace_output (OP_VOID);
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}
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@ -2621,42 +2651,14 @@ OP_5F00 ()
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switch (OP[0])
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{
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default:
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#if 0
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(*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
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State.exception = SIGILL;
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#else
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/* Use any other traps for batch debugging. */
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{
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int i;
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static int first_time = 1;
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if (first_time)
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{
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first_time = 0;
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(*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
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for (i = 0; i < 16; i++)
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(*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
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(*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
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}
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(*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
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for (i = 0; i < 16; i++)
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(*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
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for (i = 0; i < 2; i++)
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(*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
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((int)(State.a[i] >> 32) & 0xff),
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((unsigned long)State.a[i]) & 0xffffffff);
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(*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
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State.F0 != 0, State.F1 != 0, State.C != 0);
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(*d10v_callback->flush_stdout) (d10v_callback);
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break;
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uint16 vec = OP[0] + TRAP_VECTOR_START;
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BPC = PC + 1;
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move_to_cr (BPSW_CR, PSW);
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move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
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JMP (vec);
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}
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#endif
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case 0: /* old system call trap, to be deleted */
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break;
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case 15: /* new system call trap */
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/* Trap 15 is used for simulating low-level I/O */
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{
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@ -1,3 +1,10 @@
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Fri Dec 5 10:11:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S.
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* t-trap.s: New file.
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* Makefile.in (TESTS): Update.
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Thu Dec 4 16:56:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* t-macros.i: Add definitions for PSW bits.
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