mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-02-01 22:42:18 +00:00
2007-02-05 Dave Brolley <brolley@redhat.com>
* mep-*: New support for Toshiba Media Processor (MeP).
* Makefile.am: Add support for MeP.
* configure.in: Likewise.
* disassemble.c: Likewise.
* Makefile.in: Regenerated.
* configure: Regenerated.
This commit is contained in:
Dave Brolley
parent
b5057acde3
commit
bd2f2e55ad
@ -1,3 +1,12 @@
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2007-02-05 Dave Brolley <brolley@redhat.com>
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* mep-*: New support for Toshiba Media Processor (MeP).
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* Makefile.am: Add support for MeP.
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* configure.in: Likewise.
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* disassemble.c: Likewise.
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* Makefile.in: Regenerated.
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* configure: Regenerated.
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2007-02-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (OP_J): Undo the last change. Properly handle 64K
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@ -39,6 +39,7 @@ HFILES = \
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m32c-desc.h m32c-opc.h \
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m32r-desc.h m32r-opc.h \
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mcore-opc.h \
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mep-desc.h mep-opc.h \
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mt-desc.h mt-opc.h \
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openrisc-desc.h openrisc-opc.h \
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score-opc.h \
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@ -132,6 +133,11 @@ CFILES = \
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m88k-dis.c \
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maxq-dis.c \
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mcore-dis.c \
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mep-asm.c \
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mep-desc.c \
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mep-dis.c \
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mep-ibld.c \
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mep-opc.c \
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mips-dis.c \
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mips-opc.c \
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mips16-opc.c \
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@ -270,6 +276,11 @@ ALL_MACHINES = \
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m10300-opc.lo \
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maxq-dis.lo \
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mcore-dis.lo \
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mep-asm.lo \
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mep-desc.lo \
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mep-dis.lo \
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mep-ibld.lo \
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mep-opc.lo \
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mips-dis.lo \
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mips-opc.lo \
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mips16-opc.lo \
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@ -399,7 +410,7 @@ uninstall_libopcodes:
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CLEANFILES = \
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stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
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stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 stamp-xc16x\
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stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\
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libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
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@ -415,7 +426,7 @@ CGENDEPS = \
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$(CGENDIR)/opc-opinst.scm \
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cgen-asm.in cgen-dis.in cgen-ibld.in
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CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16
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CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
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if CGEN_MAINT
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IP2K_DEPS = stamp-ip2k
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@ -423,6 +434,7 @@ M32C_DEPS = stamp-m32c
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M32R_DEPS = stamp-m32r
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FR30_DEPS = stamp-fr30
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FRV_DEPS = stamp-frv
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MEP_DEPS = stamp-mep
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MT_DEPS = stamp-mt
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OPENRISC_DEPS = stamp-openrisc
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IQ2000_DEPS = stamp-iq2000
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@ -434,6 +446,7 @@ M32C_DEPS =
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M32R_DEPS =
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FR30_DEPS =
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FRV_DEPS =
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MEP_DEPS =
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MT_DEPS =
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OPENRISC_DEPS =
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IQ2000_DEPS =
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@ -507,6 +520,12 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc
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$(MAKE) run-cgen arch=frv prefix=frv options= \
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archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
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$(srcdir)/mep-desc.h $(srcdir)/mep-desc.c $(srcdir)/mep-opc.h $(srcdir)/mep-opc.c $(srcdir)/mep-ibld.c $(srcdir)/mep-asm.c $(srcdir)/mep-dis.c: $(MEP_DEPS)
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@true
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stamp-mep: $(CGENDEPS) $(CPUDIR)/mep.cpu $(CPUDIR)/mep-default.cpu $(CPUDIR)/mep-core.cpu $(CPUDIR)/mep-h1.cpu $(CPUDIR)/mep-ext-cop.cpu $(CPUDIR)/mep-sample-ucidsp.cpu $(CPUDIR)/mep-rhcop.cpu $(CPUDIR)/mep-fmax.cpu $(CPUDIR)/mep.opc
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$(MAKE) run-cgen arch=mep prefix=mep options= \
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archfile=$(CPUDIR)/mep.cpu opcfile=$(CPUDIR)/mep.opc extrafiles=
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$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS)
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@true
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stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc
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@ -928,6 +947,23 @@ maxq-dis.lo: maxq-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
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mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
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mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
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$(INCDIR)/symcat.h
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mep-asm.lo: mep-asm.c sysdep.h config.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h mep-desc.h \
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$(INCDIR)/opcode/cgen.h mep-opc.h opintl.h
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mep-desc.lo: mep-desc.c sysdep.h config.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h mep-desc.h \
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$(INCDIR)/opcode/cgen.h mep-opc.h opintl.h
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mep-dis.lo: mep-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/ansidecl.h \
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$(INCDIR)/symcat.h mep-desc.h $(INCDIR)/opcode/cgen.h \
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mep-opc.h opintl.h
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mep-ibld.lo: mep-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/ansidecl.h \
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$(INCDIR)/symcat.h mep-desc.h $(INCDIR)/opcode/cgen.h \
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mep-opc.h opintl.h
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mep-opc.lo: mep-opc.c sysdep.h config.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h mep-desc.h \
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$(INCDIR)/opcode/cgen.h mep-opc.h
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mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
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$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h \
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@ -252,6 +252,7 @@ HFILES = \
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m32c-desc.h m32c-opc.h \
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m32r-desc.h m32r-opc.h \
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mcore-opc.h \
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mep-desc.h mep-opc.h \
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mt-desc.h mt-opc.h \
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openrisc-desc.h openrisc-opc.h \
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score-opc.h \
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@ -346,6 +347,11 @@ CFILES = \
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m88k-dis.c \
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maxq-dis.c \
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mcore-dis.c \
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mep-asm.c \
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mep-desc.c \
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mep-dis.c \
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mep-ibld.c \
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mep-opc.c \
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mips-dis.c \
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mips-opc.c \
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mips16-opc.c \
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@ -484,6 +490,11 @@ ALL_MACHINES = \
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m10300-opc.lo \
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maxq-dis.lo \
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mcore-dis.lo \
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mep-asm.lo \
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mep-desc.lo \
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mep-dis.lo \
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mep-ibld.lo \
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mep-opc.lo \
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mips-dis.lo \
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mips-opc.lo \
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mips16-opc.lo \
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@ -567,7 +578,7 @@ noinst_LIBRARIES = libopcodes.a
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POTFILES = $(HFILES) $(CFILES)
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CLEANFILES = \
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stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
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stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 stamp-xc16x\
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stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\
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libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
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CGENDIR = @cgendir@
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@ -581,7 +592,7 @@ CGENDEPS = \
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$(CGENDIR)/opc-opinst.scm \
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cgen-asm.in cgen-dis.in cgen-ibld.in
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CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16
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CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
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@CGEN_MAINT_FALSE@IP2K_DEPS =
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@CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k
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@CGEN_MAINT_FALSE@M32C_DEPS =
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@ -592,6 +603,8 @@ CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16
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@CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
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@CGEN_MAINT_FALSE@FRV_DEPS =
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@CGEN_MAINT_TRUE@FRV_DEPS = stamp-frv
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@CGEN_MAINT_FALSE@MEP_DEPS =
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@CGEN_MAINT_TRUE@MEP_DEPS = stamp-mep
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@CGEN_MAINT_FALSE@MT_DEPS =
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@CGEN_MAINT_TRUE@MT_DEPS = stamp-mt
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@CGEN_MAINT_FALSE@OPENRISC_DEPS =
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@ -1044,6 +1057,12 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc
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$(MAKE) run-cgen arch=frv prefix=frv options= \
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archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
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$(srcdir)/mep-desc.h $(srcdir)/mep-desc.c $(srcdir)/mep-opc.h $(srcdir)/mep-opc.c $(srcdir)/mep-ibld.c $(srcdir)/mep-asm.c $(srcdir)/mep-dis.c: $(MEP_DEPS)
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@true
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stamp-mep: $(CGENDEPS) $(CPUDIR)/mep.cpu $(CPUDIR)/mep-default.cpu $(CPUDIR)/mep-core.cpu $(CPUDIR)/mep-h1.cpu $(CPUDIR)/mep-ext-cop.cpu $(CPUDIR)/mep-sample-ucidsp.cpu $(CPUDIR)/mep-rhcop.cpu $(CPUDIR)/mep-fmax.cpu $(CPUDIR)/mep.opc
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$(MAKE) run-cgen arch=mep prefix=mep options= \
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archfile=$(CPUDIR)/mep.cpu opcfile=$(CPUDIR)/mep.opc extrafiles=
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$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS)
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@true
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stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc
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@ -1465,6 +1484,23 @@ maxq-dis.lo: maxq-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
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mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
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mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
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$(INCDIR)/symcat.h
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mep-asm.lo: mep-asm.c sysdep.h config.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h mep-desc.h \
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$(INCDIR)/opcode/cgen.h mep-opc.h opintl.h
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mep-desc.lo: mep-desc.c sysdep.h config.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h mep-desc.h \
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$(INCDIR)/opcode/cgen.h mep-opc.h opintl.h
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mep-dis.lo: mep-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/ansidecl.h \
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$(INCDIR)/symcat.h mep-desc.h $(INCDIR)/opcode/cgen.h \
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mep-opc.h opintl.h
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mep-ibld.lo: mep-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \
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$(BFD_H) $(INCDIR)/ansidecl.h \
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$(INCDIR)/symcat.h mep-desc.h $(INCDIR)/opcode/cgen.h \
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mep-opc.h opintl.h
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mep-opc.lo: mep-opc.c sysdep.h config.h $(BFD_H) \
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$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h mep-desc.h \
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$(INCDIR)/opcode/cgen.h mep-opc.h
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mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
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$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h \
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1
opcodes/configure
vendored
1
opcodes/configure
vendored
@ -6555,6 +6555,7 @@ if test x${all_targets} = xfalse ; then
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bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
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bfd_maxq_arch) ta="$ta maxq-dis.lo" ;;
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bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
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bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
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bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
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bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
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bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
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@ -184,6 +184,7 @@ if test x${all_targets} = xfalse ; then
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bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
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bfd_maxq_arch) ta="$ta maxq-dis.lo" ;;
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bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
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bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
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bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
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bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
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bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
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@ -50,6 +50,7 @@
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#define ARCH_m88k
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#define ARCH_maxq
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#define ARCH_mcore
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#define ARCH_mep
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#define ARCH_mips
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#define ARCH_mmix
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#define ARCH_mn10200
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@ -261,6 +262,11 @@ disassembler (abfd)
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disassemble = print_insn_mcore;
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break;
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#endif
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#ifdef ARCH_mep
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case bfd_arch_mep:
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disassemble = print_insn_mep;
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break;
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#endif
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#ifdef ARCH_mips
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case bfd_arch_mips:
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if (bfd_big_endian (abfd))
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@ -479,6 +485,12 @@ disassemble_init_for_target (struct disassemble_info * info)
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info->skip_zeroes = 32;
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break;
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#endif
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#ifdef ARCH_mep
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case bfd_arch_mep:
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info->skip_zeroes = 256;
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info->skip_zeroes_at_end = 0;
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break;
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#endif
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#ifdef ARCH_m32c
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case bfd_arch_m32c:
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info->endian = BFD_ENDIAN_BIG;
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1398
opcodes/mep-asm.c
Normal file
1398
opcodes/mep-asm.c
Normal file
File diff suppressed because it is too large
Load Diff
2729
opcodes/mep-desc.c
Normal file
2729
opcodes/mep-desc.c
Normal file
File diff suppressed because it is too large
Load Diff
342
opcodes/mep-desc.h
Normal file
342
opcodes/mep-desc.h
Normal file
@ -0,0 +1,342 @@
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/* CPU data header for mep.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2005 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef MEP_CPU_H
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#define MEP_CPU_H
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|
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#include "opcode/cgen-bitset.h"
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|
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#define CGEN_ARCH mep
|
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|
||||
/* Given symbol S, return mep_cgen_<S>. */
|
||||
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
|
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#define CGEN_SYM(s) mep##_cgen_##s
|
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#else
|
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#define CGEN_SYM(s) mep/**/_cgen_/**/s
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#endif
|
||||
|
||||
|
||||
/* Selected cpu families. */
|
||||
#define HAVE_CPU_MEPF
|
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|
||||
#define CGEN_INSN_LSB0_P 0
|
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|
||||
/* Minimum size of any insn (in bytes). */
|
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#define CGEN_MIN_INSN_SIZE 2
|
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|
||||
/* Maximum size of any insn (in bytes). */
|
||||
#define CGEN_MAX_INSN_SIZE 4
|
||||
|
||||
#define CGEN_INT_INSN_P 1
|
||||
|
||||
/* Maximum number of syntax elements in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17
|
||||
|
||||
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
|
||||
we can't hash on everything up to the space. */
|
||||
#define CGEN_MNEMONIC_OPERANDS
|
||||
|
||||
/* Maximum number of fields in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11
|
||||
|
||||
/* Enums. */
|
||||
|
||||
/* Enum declaration for major opcodes. */
|
||||
typedef enum major {
|
||||
MAJ_0, MAJ_1, MAJ_2, MAJ_3
|
||||
, MAJ_4, MAJ_5, MAJ_6, MAJ_7
|
||||
, MAJ_8, MAJ_9, MAJ_10, MAJ_11
|
||||
, MAJ_12, MAJ_13, MAJ_14, MAJ_15
|
||||
} MAJOR;
|
||||
|
||||
/* Enum declaration for condition opcode enum. */
|
||||
typedef enum fmax_cond {
|
||||
FMAX_F, FMAX_U, FMAX_E, FMAX_UE
|
||||
, FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE
|
||||
, FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI
|
||||
, FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI
|
||||
} FMAX_COND;
|
||||
|
||||
/* Attributes. */
|
||||
|
||||
/* Enum declaration for machine type selection. */
|
||||
typedef enum mach_attr {
|
||||
MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
|
||||
} MACH_ATTR;
|
||||
|
||||
/* Enum declaration for instruction set selection. */
|
||||
typedef enum isa_attr {
|
||||
ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16
|
||||
, ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX
|
||||
} ISA_ATTR;
|
||||
|
||||
/* Enum declaration for datatype to use for C intrinsics mapping. */
|
||||
typedef enum cdata_attr {
|
||||
CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT
|
||||
, CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT
|
||||
, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
|
||||
} CDATA_ATTR;
|
||||
|
||||
/* Enum declaration for . */
|
||||
typedef enum config_attr {
|
||||
CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX
|
||||
} CONFIG_ATTR;
|
||||
|
||||
/* Number of architecture variants. */
|
||||
#define MAX_ISAS ((int) ISA_MAX)
|
||||
#define MAX_MACHS ((int) MACH_MAX)
|
||||
|
||||
/* Ifield support. */
|
||||
|
||||
/* Ifield attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_ifld attrs. */
|
||||
typedef enum cgen_ifld_attr {
|
||||
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
|
||||
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
|
||||
, CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
|
||||
} CGEN_IFLD_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_ifld_attr. */
|
||||
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_ifld attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
|
||||
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
|
||||
|
||||
/* Enum declaration for mep ifield types. */
|
||||
typedef enum ifield_type {
|
||||
MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
|
||||
, MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
|
||||
, MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN
|
||||
, MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI
|
||||
, MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1
|
||||
, MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5
|
||||
, MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9
|
||||
, MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13
|
||||
, MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17
|
||||
, MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21
|
||||
, MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25
|
||||
, MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29
|
||||
, MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2
|
||||
, MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N
|
||||
, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6
|
||||
, MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16
|
||||
, MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8
|
||||
, MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16
|
||||
, MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2
|
||||
, MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
|
||||
, MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
|
||||
, MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
|
||||
, MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4
|
||||
, MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4
|
||||
, MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1
|
||||
, MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN
|
||||
, MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX
|
||||
} IFIELD_TYPE;
|
||||
|
||||
#define MAX_IFLD ((int) MEP_F_MAX)
|
||||
|
||||
/* Hardware attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_hw attrs. */
|
||||
typedef enum cgen_hw_attr {
|
||||
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
|
||||
, CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH
|
||||
, CGEN_HW_ISA, CGEN_HW_END_NBOOLS
|
||||
} CGEN_HW_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_hw_attr. */
|
||||
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_hw attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
|
||||
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0)
|
||||
|
||||
/* Enum declaration for mep hardware types. */
|
||||
typedef enum cgen_hw_type {
|
||||
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
||||
, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
|
||||
, HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX
|
||||
, HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX
|
||||
} CGEN_HW_TYPE;
|
||||
|
||||
#define MAX_HW ((int) HW_MAX)
|
||||
|
||||
/* Operand attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_operand attrs. */
|
||||
typedef enum cgen_operand_attr {
|
||||
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
|
||||
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
|
||||
, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
|
||||
, CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS
|
||||
} CGEN_OPERAND_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_operand_attr. */
|
||||
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_operand attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0)
|
||||
|
||||
/* Enum declaration for mep operand types. */
|
||||
typedef enum cgen_operand_type {
|
||||
MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM
|
||||
, MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC
|
||||
, MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL
|
||||
, MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S
|
||||
, MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP
|
||||
, MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0
|
||||
, MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW
|
||||
, MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG
|
||||
, MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP
|
||||
, MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN
|
||||
, MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64
|
||||
, MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2
|
||||
, MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2
|
||||
, MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16
|
||||
, MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8
|
||||
, MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
|
||||
, MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
|
||||
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
|
||||
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
|
||||
, MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD
|
||||
, MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT
|
||||
, MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR
|
||||
, MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX
|
||||
} CGEN_OPERAND_TYPE;
|
||||
|
||||
/* Number of operands types. */
|
||||
#define MAX_OPERANDS 90
|
||||
|
||||
/* Maximum number of operands referenced by any insn. */
|
||||
#define MAX_OPERAND_INSTANCES 8
|
||||
|
||||
/* Insn attribute indices. */
|
||||
|
||||
/* Enum declaration for cgen_insn attrs. */
|
||||
typedef enum cgen_insn_attr {
|
||||
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
|
||||
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
|
||||
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN
|
||||
, CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN
|
||||
, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN
|
||||
, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN
|
||||
, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
|
||||
, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
|
||||
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
|
||||
, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS
|
||||
} CGEN_INSN_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_insn_attr. */
|
||||
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_insn attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0)
|
||||
|
||||
/* cgen.h uses things we just defined. */
|
||||
#include "opcode/cgen.h"
|
||||
|
||||
extern const struct cgen_ifld mep_cgen_ifld_table[];
|
||||
|
||||
/* Attributes. */
|
||||
extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[];
|
||||
|
||||
/* Hardware decls. */
|
||||
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_gpr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_csr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_cr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax;
|
||||
|
||||
extern const CGEN_HW_ENTRY mep_cgen_hw_table[];
|
||||
|
||||
|
||||
|
||||
#endif /* MEP_CPU_H */
|
||||
1205
opcodes/mep-dis.c
Normal file
1205
opcodes/mep-dis.c
Normal file
File diff suppressed because it is too large
Load Diff
2541
opcodes/mep-ibld.c
Normal file
2541
opcodes/mep-ibld.c
Normal file
File diff suppressed because it is too large
Load Diff
2274
opcodes/mep-opc.c
Normal file
2274
opcodes/mep-opc.c
Normal file
File diff suppressed because it is too large
Load Diff
294
opcodes/mep-opc.h
Normal file
294
opcodes/mep-opc.h
Normal file
@ -0,0 +1,294 @@
|
||||
/* Instruction opcode header for mep.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright 1996-2005 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef MEP_OPC_H
|
||||
#define MEP_OPC_H
|
||||
|
||||
/* -- opc.h */
|
||||
|
||||
#undef CGEN_DIS_HASH_SIZE
|
||||
#define CGEN_DIS_HASH_SIZE 1
|
||||
|
||||
#undef CGEN_DIS_HASH
|
||||
#define CGEN_DIS_HASH(buffer, insn) 0
|
||||
|
||||
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char * name;
|
||||
int config_enum;
|
||||
unsigned cpu_flag;
|
||||
int big_endian;
|
||||
int vliw_bits;
|
||||
CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa;
|
||||
CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa;
|
||||
CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa;
|
||||
CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa;
|
||||
CGEN_ATTR_VALUE_BITSET_TYPE cop_isa;
|
||||
CGEN_ATTR_VALUE_BITSET_TYPE core_isa;
|
||||
unsigned int option_mask;
|
||||
} mep_config_map_struct;
|
||||
|
||||
extern mep_config_map_struct mep_config_map[];
|
||||
extern int mep_config_index;
|
||||
|
||||
extern void init_mep_all_core_isas_mask (void);
|
||||
extern void init_mep_all_cop_isas_mask (void);
|
||||
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void);
|
||||
|
||||
#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum)
|
||||
#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag)
|
||||
#define MEP_OMASK (mep_config_map[mep_config_index].option_mask)
|
||||
#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0)
|
||||
#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32)
|
||||
#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64)
|
||||
#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa)
|
||||
#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa)
|
||||
#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa)
|
||||
#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa)
|
||||
#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa)
|
||||
#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa)
|
||||
|
||||
extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *);
|
||||
|
||||
/* A mask for all ISAs executed by the core. */
|
||||
#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask
|
||||
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask;
|
||||
|
||||
#define MEP_INSN_CORE_P(insn) ( \
|
||||
init_mep_all_core_isas_mask (), \
|
||||
mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \
|
||||
)
|
||||
|
||||
/* A mask for all ISAs executed by a VLIW coprocessor. */
|
||||
#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
|
||||
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
|
||||
|
||||
#define MEP_INSN_COP_P(insn) ( \
|
||||
init_mep_all_cop_isas_mask (), \
|
||||
mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \
|
||||
)
|
||||
|
||||
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
|
||||
|
||||
/* -- asm.c */
|
||||
/* Enum declaration for mep instruction types. */
|
||||
typedef enum cgen_insn_type {
|
||||
MEP_INSN_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW
|
||||
, MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU
|
||||
, MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP
|
||||
, MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP
|
||||
, MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16
|
||||
, MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16
|
||||
, MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24
|
||||
, MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB
|
||||
, MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8
|
||||
, MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH
|
||||
, MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3
|
||||
, MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3
|
||||
, MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3
|
||||
, MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X
|
||||
, MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR
|
||||
, MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA
|
||||
, MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI
|
||||
, MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA
|
||||
, MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI
|
||||
, MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE
|
||||
, MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24
|
||||
, MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT
|
||||
, MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC
|
||||
, MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC
|
||||
, MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT
|
||||
, MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM
|
||||
, MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM
|
||||
, MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE
|
||||
, MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU
|
||||
, MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU
|
||||
, MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK
|
||||
, MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN
|
||||
, MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP
|
||||
, MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU
|
||||
, MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP
|
||||
, MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI
|
||||
, MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16
|
||||
, MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA
|
||||
, MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA
|
||||
, MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0
|
||||
, MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0
|
||||
, MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1
|
||||
, MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1
|
||||
, MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT
|
||||
, MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV
|
||||
, MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2
|
||||
, MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6
|
||||
, MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10
|
||||
, MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14
|
||||
, MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21
|
||||
, MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25
|
||||
, MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19
|
||||
, MEP_INSN_FADDS, MEP_INSN_FSUBS, MEP_INSN_FMULS, MEP_INSN_FDIVS
|
||||
, MEP_INSN_FSQRTS, MEP_INSN_FABSS, MEP_INSN_FNEGS, MEP_INSN_FMOVS
|
||||
, MEP_INSN_FROUNDWS, MEP_INSN_FTRUNCWS, MEP_INSN_FCEILWS, MEP_INSN_FFLOORWS
|
||||
, MEP_INSN_FCVTWS, MEP_INSN_FCVTSW, MEP_INSN_FCMPFS, MEP_INSN_FCMPUS
|
||||
, MEP_INSN_FCMPES, MEP_INSN_FCMPUES, MEP_INSN_FCMPLS, MEP_INSN_FCMPULS
|
||||
, MEP_INSN_FCMPLES, MEP_INSN_FCMPULES, MEP_INSN_FCMPFIS, MEP_INSN_FCMPUIS
|
||||
, MEP_INSN_FCMPEIS, MEP_INSN_FCMPUEIS, MEP_INSN_FCMPLIS, MEP_INSN_FCMPULIS
|
||||
, MEP_INSN_FCMPLEIS, MEP_INSN_FCMPULEIS, MEP_INSN_CMOV_FRN_RM, MEP_INSN_CMOV_RM_FRN
|
||||
, MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RM_CCRN
|
||||
} CGEN_INSN_TYPE;
|
||||
|
||||
/* Index of `invalid' insn place holder. */
|
||||
#define CGEN_INSN_INVALID MEP_INSN_INVALID
|
||||
|
||||
/* Total number of insns in table. */
|
||||
#define MAX_INSNS ((int) MEP_INSN_CMOVC_RM_CCRN + 1)
|
||||
|
||||
/* This struct records data prior to insertion or after extraction. */
|
||||
struct cgen_fields
|
||||
{
|
||||
int length;
|
||||
long f_nil;
|
||||
long f_anyof;
|
||||
long f_major;
|
||||
long f_rn;
|
||||
long f_rn3;
|
||||
long f_rm;
|
||||
long f_rl;
|
||||
long f_sub2;
|
||||
long f_sub3;
|
||||
long f_sub4;
|
||||
long f_ext;
|
||||
long f_crn;
|
||||
long f_csrn_hi;
|
||||
long f_csrn_lo;
|
||||
long f_csrn;
|
||||
long f_crnx_hi;
|
||||
long f_crnx_lo;
|
||||
long f_crnx;
|
||||
long f_0;
|
||||
long f_1;
|
||||
long f_2;
|
||||
long f_3;
|
||||
long f_4;
|
||||
long f_5;
|
||||
long f_6;
|
||||
long f_7;
|
||||
long f_8;
|
||||
long f_9;
|
||||
long f_10;
|
||||
long f_11;
|
||||
long f_12;
|
||||
long f_13;
|
||||
long f_14;
|
||||
long f_15;
|
||||
long f_16;
|
||||
long f_17;
|
||||
long f_18;
|
||||
long f_19;
|
||||
long f_20;
|
||||
long f_21;
|
||||
long f_22;
|
||||
long f_23;
|
||||
long f_24;
|
||||
long f_25;
|
||||
long f_26;
|
||||
long f_27;
|
||||
long f_28;
|
||||
long f_29;
|
||||
long f_30;
|
||||
long f_31;
|
||||
long f_8s8a2;
|
||||
long f_12s4a2;
|
||||
long f_17s16a2;
|
||||
long f_24s5a2n_hi;
|
||||
long f_24s5a2n_lo;
|
||||
long f_24s5a2n;
|
||||
long f_24u5a2n_hi;
|
||||
long f_24u5a2n_lo;
|
||||
long f_24u5a2n;
|
||||
long f_2u6;
|
||||
long f_7u9;
|
||||
long f_7u9a2;
|
||||
long f_7u9a4;
|
||||
long f_16s16;
|
||||
long f_2u10;
|
||||
long f_3u5;
|
||||
long f_4u8;
|
||||
long f_5u8;
|
||||
long f_5u24;
|
||||
long f_6s8;
|
||||
long f_8s8;
|
||||
long f_16u16;
|
||||
long f_12u16;
|
||||
long f_3u29;
|
||||
long f_8s24;
|
||||
long f_8s24a2;
|
||||
long f_8s24a4;
|
||||
long f_8s24a8;
|
||||
long f_24u8a4n_hi;
|
||||
long f_24u8a4n_lo;
|
||||
long f_24u8a4n;
|
||||
long f_24u8n_hi;
|
||||
long f_24u8n_lo;
|
||||
long f_24u8n;
|
||||
long f_24u4n_hi;
|
||||
long f_24u4n_lo;
|
||||
long f_24u4n;
|
||||
long f_callnum;
|
||||
long f_ccrn_hi;
|
||||
long f_ccrn_lo;
|
||||
long f_ccrn;
|
||||
long f_fmax_0_4;
|
||||
long f_fmax_4_4;
|
||||
long f_fmax_8_4;
|
||||
long f_fmax_12_4;
|
||||
long f_fmax_16_4;
|
||||
long f_fmax_20_4;
|
||||
long f_fmax_24_4;
|
||||
long f_fmax_28_1;
|
||||
long f_fmax_29_1;
|
||||
long f_fmax_30_1;
|
||||
long f_fmax_31_1;
|
||||
long f_fmax_frd;
|
||||
long f_fmax_frn;
|
||||
long f_fmax_frm;
|
||||
long f_fmax_rm;
|
||||
};
|
||||
|
||||
#define CGEN_INIT_PARSE(od) \
|
||||
{\
|
||||
}
|
||||
#define CGEN_INIT_INSERT(od) \
|
||||
{\
|
||||
}
|
||||
#define CGEN_INIT_EXTRACT(od) \
|
||||
{\
|
||||
}
|
||||
#define CGEN_INIT_PRINT(od) \
|
||||
{\
|
||||
}
|
||||
|
||||
|
||||
#endif /* MEP_OPC_H */
|
||||
Loading…
x
Reference in New Issue
Block a user