mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2025-01-18 23:13:46 +00:00
2009-09-23 Michael Eager <eager@eagercon.com>
* configure: Add microblaze-*.* (not regenerated).
* configure.ac: Likewise.
* microblaze/config.in: New.
* microblaze/configure: Generate.
* microblaze/configure.ac: New.
* microblaze/interp.c: New.
* microblaze/Makefile.in: New.
* microblaze/microblaze.h: New.
* microblaze/microblaze.isa: New.
* microblaze/sim-main.h: New.
* microblaze/sysdep.h: New.
This commit is contained in:
Michael Eager
parent
572771db36
commit
bd30e45a34
@ -1,3 +1,17 @@
|
||||
2009-09-23 Michael Eager <eager@eagercon.com>
|
||||
|
||||
* configure: Add microblaze-*.* (not regenerated).
|
||||
* configure.ac: Likewise.
|
||||
* microblaze/config.in: New.
|
||||
* microblaze/configure: Generate.
|
||||
* microblaze/configure.ac: New.
|
||||
* microblaze/interp.c: New.
|
||||
* microblaze/Makefile.in: New.
|
||||
* microblaze/microblaze.h: New.
|
||||
* microblaze/microblaze.isa: New.
|
||||
* microblaze/sim-main.h: New.
|
||||
* microblaze/sysdep.h: New.
|
||||
|
||||
2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
||||
|
||||
* avr/config.in: Regenerate.
|
||||
|
||||
6
sim/configure
vendored
6
sim/configure
vendored
@ -646,6 +646,7 @@ m32c
|
||||
m32r
|
||||
m68hc11
|
||||
mcore
|
||||
microblaze
|
||||
mips
|
||||
mn10300
|
||||
moxie
|
||||
@ -3676,6 +3677,11 @@ subdirs="$subdirs arm"
|
||||
mcore-*-*)
|
||||
subdirs="$subdirs mcore"
|
||||
|
||||
testsuite=yes
|
||||
;;
|
||||
microblaze-*-*)
|
||||
subdirs="$subdirs microblaze"
|
||||
|
||||
testsuite=yes
|
||||
;;
|
||||
mips*-*-*)
|
||||
|
||||
@ -97,6 +97,10 @@ if test "${enable_sim}" != no; then
|
||||
AC_CONFIG_SUBDIRS(mcore)
|
||||
testsuite=yes
|
||||
;;
|
||||
microblaze-*-*)
|
||||
AC_CONFIG_SUBDIRS(microblaze)
|
||||
testsuite=yes
|
||||
;;
|
||||
mips*-*-*)
|
||||
AC_CONFIG_SUBDIRS(mips)
|
||||
testsuite=yes
|
||||
|
||||
29
sim/microblaze/Makefile.in
Normal file
29
sim/microblaze/Makefile.in
Normal file
@ -0,0 +1,29 @@
|
||||
# Makefile template for Configure for the MCore sim library.
|
||||
# Copyright (C) 1990, 91, 92, 95, 96, 19, 1999, 2007, 2008, 2009
|
||||
# Free Software Foundation, Inc.
|
||||
# Written by Cygnus Solutions.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
## COMMON_PRE_CONFIG_FRAG
|
||||
|
||||
SIM_OBJS = interp.o sim-load.o
|
||||
SIM_EXTRA_LIBS = -lm
|
||||
SIM_EXTRA_CLEAN = microblaze-clean
|
||||
|
||||
## COMMON_POST_CONFIG_FRAG
|
||||
|
||||
interp.o: interp.c
|
||||
|
||||
microblaze-clean:
|
||||
104
sim/microblaze/config.in
Normal file
104
sim/microblaze/config.in
Normal file
@ -0,0 +1,104 @@
|
||||
/* config.in. Generated from configure.ac by autoheader. */
|
||||
|
||||
/* Define to 1 if translation of program messages to the user's native
|
||||
language is requested. */
|
||||
#undef ENABLE_NLS
|
||||
|
||||
/* Define to 1 if you have the <dlfcn.h> header file. */
|
||||
#undef HAVE_DLFCN_H
|
||||
|
||||
/* Define to 1 if you have the <errno.h> header file. */
|
||||
#undef HAVE_ERRNO_H
|
||||
|
||||
/* Define to 1 if you have the <fcntl.h> header file. */
|
||||
#undef HAVE_FCNTL_H
|
||||
|
||||
/* Define to 1 if you have the <fpu_control.h> header file. */
|
||||
#undef HAVE_FPU_CONTROL_H
|
||||
|
||||
/* Define to 1 if you have the `getrusage' function. */
|
||||
#undef HAVE_GETRUSAGE
|
||||
|
||||
/* Define to 1 if you have the <inttypes.h> header file. */
|
||||
#undef HAVE_INTTYPES_H
|
||||
|
||||
/* Define to 1 if you have the `nsl' library (-lnsl). */
|
||||
#undef HAVE_LIBNSL
|
||||
|
||||
/* Define to 1 if you have the `socket' library (-lsocket). */
|
||||
#undef HAVE_LIBSOCKET
|
||||
|
||||
/* Define to 1 if you have the <memory.h> header file. */
|
||||
#undef HAVE_MEMORY_H
|
||||
|
||||
/* Define to 1 if you have the `sigaction' function. */
|
||||
#undef HAVE_SIGACTION
|
||||
|
||||
/* Define to 1 if you have the <stdint.h> header file. */
|
||||
#undef HAVE_STDINT_H
|
||||
|
||||
/* Define to 1 if you have the <stdlib.h> header file. */
|
||||
#undef HAVE_STDLIB_H
|
||||
|
||||
/* Define to 1 if you have the <strings.h> header file. */
|
||||
#undef HAVE_STRINGS_H
|
||||
|
||||
/* Define to 1 if you have the <string.h> header file. */
|
||||
#undef HAVE_STRING_H
|
||||
|
||||
/* Define to 1 if you have the <sys/resource.h> header file. */
|
||||
#undef HAVE_SYS_RESOURCE_H
|
||||
|
||||
/* Define to 1 if you have the <sys/stat.h> header file. */
|
||||
#undef HAVE_SYS_STAT_H
|
||||
|
||||
/* Define to 1 if you have the <sys/time.h> header file. */
|
||||
#undef HAVE_SYS_TIME_H
|
||||
|
||||
/* Define to 1 if you have the <sys/types.h> header file. */
|
||||
#undef HAVE_SYS_TYPES_H
|
||||
|
||||
/* Define to 1 if you have the `time' function. */
|
||||
#undef HAVE_TIME
|
||||
|
||||
/* Define to 1 if you have the <time.h> header file. */
|
||||
#undef HAVE_TIME_H
|
||||
|
||||
/* Define to 1 if you have the <unistd.h> header file. */
|
||||
#undef HAVE_UNISTD_H
|
||||
|
||||
/* Define to 1 if you have the <zlib.h> header file. */
|
||||
#undef HAVE_ZLIB_H
|
||||
|
||||
/* Define to 1 if you have the `__setfpucw' function. */
|
||||
#undef HAVE___SETFPUCW
|
||||
|
||||
/* Define to the address where bug reports for this package should be sent. */
|
||||
#undef PACKAGE_BUGREPORT
|
||||
|
||||
/* Define to the full name of this package. */
|
||||
#undef PACKAGE_NAME
|
||||
|
||||
/* Define to the full name and version of this package. */
|
||||
#undef PACKAGE_STRING
|
||||
|
||||
/* Define to the one symbol short name of this package. */
|
||||
#undef PACKAGE_TARNAME
|
||||
|
||||
/* Define to the home page for this package. */
|
||||
#undef PACKAGE_URL
|
||||
|
||||
/* Define to the version of this package. */
|
||||
#undef PACKAGE_VERSION
|
||||
|
||||
/* Additional package description */
|
||||
#undef PKGVERSION
|
||||
|
||||
/* Bug reporting address */
|
||||
#undef REPORT_BUGS_TO
|
||||
|
||||
/* Define as the return type of signal handlers (`int' or `void'). */
|
||||
#undef RETSIGTYPE
|
||||
|
||||
/* Define to 1 if you have the ANSI C header files. */
|
||||
#undef STDC_HEADERS
|
||||
7004
sim/microblaze/configure
vendored
Normal file
7004
sim/microblaze/configure
vendored
Normal file
File diff suppressed because it is too large
Load Diff
14
sim/microblaze/configure.ac
Normal file
14
sim/microblaze/configure.ac
Normal file
@ -0,0 +1,14 @@
|
||||
dnl Process this file with autoconf to produce a configure script.
|
||||
AC_PREREQ(2.59)dnl
|
||||
AC_INIT(Makefile.in)
|
||||
AC_CONFIG_HEADER(config.h:config.in)
|
||||
|
||||
sinclude(../common/aclocal.m4)
|
||||
|
||||
# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
|
||||
# it by inlining the macro's contents.
|
||||
sinclude(../common/common.m4)
|
||||
|
||||
AC_CHECK_HEADERS(unistd.h)
|
||||
|
||||
SIM_AC_OUTPUT
|
||||
1090
sim/microblaze/interp.c
Normal file
1090
sim/microblaze/interp.c
Normal file
File diff suppressed because it is too large
Load Diff
106
sim/microblaze/microblaze.h
Normal file
106
sim/microblaze/microblaze.h
Normal file
@ -0,0 +1,106 @@
|
||||
#ifndef MICROBLAZE_H
|
||||
#define MICROBLAZE_H
|
||||
|
||||
/* Copyright 2009 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the Xilinx MicroBlaze simulator.
|
||||
|
||||
This library is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#include "../../opcodes/microblaze-opcm.h"
|
||||
|
||||
#define GET_RD ((inst & RD_MASK) >> RD_LOW)
|
||||
#define GET_RA ((inst & RA_MASK) >> RA_LOW)
|
||||
#define GET_RB ((inst & RB_MASK) >> RB_LOW)
|
||||
|
||||
#define CPU microblaze_state.cpu[0].microblaze_cpu
|
||||
|
||||
#define RD CPU.regs[rd]
|
||||
#define RA CPU.regs[ra]
|
||||
#define RB CPU.regs[rb]
|
||||
/* #define IMM immword */
|
||||
|
||||
#define SA CPU.spregs[IMM & 0x1]
|
||||
|
||||
#define IMM_H CPU.imm_high
|
||||
#define IMM_L ((inst & IMM_MASK) >> IMM_LOW)
|
||||
|
||||
#define IMM_ENABLE CPU.imm_enable
|
||||
|
||||
#define IMM (IMM_ENABLE ? \
|
||||
(((uhalf)IMM_H << 16) | (uhalf)IMM_L) : \
|
||||
(imm_unsigned ? \
|
||||
(0xFFFF & IMM_L) : \
|
||||
(IMM_L & 0x8000 ? \
|
||||
(0xFFFF0000 | IMM_L) : \
|
||||
(0x0000FFFF & IMM_L))))
|
||||
|
||||
#define PC CPU.spregs[0]
|
||||
#define MSR CPU.spregs[1]
|
||||
#define SP CPU.regs[29]
|
||||
#define RETREG CPU.regs[3]
|
||||
|
||||
|
||||
#define MEM(X) memory[X]
|
||||
|
||||
#define MEM_RD_BYTE(X) rbat(X)
|
||||
#define MEM_RD_HALF(X) rhat(X)
|
||||
#define MEM_RD_WORD(X) rlat(X)
|
||||
#define MEM_RD_UBYTE(X) (ubyte) MEM_RD_BYTE(X)
|
||||
#define MEM_RD_UHALF(X) (uhalf) MEM_RD_HALF(X)
|
||||
#define MEM_RD_UWORD(X) (uword) MEM_RD_WORD(X)
|
||||
|
||||
#define MEM_WR_BYTE(X, D) wbat(X, D)
|
||||
#define MEM_WR_HALF(X, D) what(X, D)
|
||||
#define MEM_WR_WORD(X, D) wlat(X, D)
|
||||
|
||||
|
||||
#define MICROBLAZE_SEXT8(X) ((char) X)
|
||||
#define MICROBLAZE_SEXT16(X) ((short) X)
|
||||
|
||||
|
||||
#define CARRY carry
|
||||
#define C_rd ((MSR & 0x4) >> 2)
|
||||
#define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
|
||||
|
||||
#define C_calc(X, Y, C) ((((uword)Y == MAX_WORD) && (C == 1)) ? \
|
||||
1 : \
|
||||
((MAX_WORD - (uword)X) < ((uword)Y + C)))
|
||||
|
||||
#define BIP_MASK 0x00000008
|
||||
#define CARRY_MASK 0x00000004
|
||||
#define INTR_EN_MASK 0x00000002
|
||||
#define BUSLOCK_MASK 0x00000001
|
||||
|
||||
#define DELAY_SLOT delay_slot_enable = 1
|
||||
#define BRANCH branch_taken = 1
|
||||
|
||||
#define NUM_REGS 32
|
||||
#define NUM_SPECIAL 2
|
||||
#define INST_SIZE 4
|
||||
|
||||
#define MAX_WORD 0xFFFFFFFF
|
||||
#define MICROBLAZE_HALT_INST 0xb8000000
|
||||
|
||||
typedef char byte;
|
||||
typedef short half;
|
||||
typedef int word;
|
||||
typedef unsigned char ubyte;
|
||||
typedef unsigned short uhalf;
|
||||
typedef unsigned int uword;
|
||||
|
||||
#endif /* MICROBLAZE_H */
|
||||
|
||||
823
sim/microblaze/microblaze.isa
Normal file
823
sim/microblaze/microblaze.isa
Normal file
@ -0,0 +1,823 @@
|
||||
/* Copyright 2009 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the Xilinx MicroBlaze simulator.
|
||||
|
||||
This library is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
/*
|
||||
* MICROBLAZE Instruction Set Architecture
|
||||
*
|
||||
* INSTRUCTION(NAME,
|
||||
* OPCODE,
|
||||
* TYPE,
|
||||
* SEMANTICS)
|
||||
*
|
||||
*/
|
||||
|
||||
INSTRUCTION(add,
|
||||
0x00,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
CARRY = C_calc(RA, RB, 0);
|
||||
RD = RA + RB;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsub,
|
||||
0x01,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
CARRY = C_calc(RB, ~RA, 1);
|
||||
RD = RB + ~RA + 1;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(addc,
|
||||
0x02,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
CARRY = C_calc(RA, RB, C_rd);
|
||||
RD = RA + RB + C_rd;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubc,
|
||||
0x03,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
CARRY = C_calc(RB, ~RA, C_rd);
|
||||
RD = RB + ~RA + C_rd;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(addk,
|
||||
0x04,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA + RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubk,
|
||||
0x05,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RB + ~RA + 1;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(cmp,
|
||||
0x05,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
{
|
||||
int tmp_reg = RB + ~RA + 1;
|
||||
if ((RB & 0x80000000) ^ (RA & 0x80000000)) {
|
||||
tmp_reg = ((tmp_reg & 0x7fffffff) | (RB & 0x80000000));
|
||||
}
|
||||
RD = tmp_reg;
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(cmpu,
|
||||
0x05,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
{
|
||||
int tmp_reg = RB + ~RA + 1;
|
||||
if ((RB & 0x80000000) ^ (RA & 0x80000000)) {
|
||||
tmp_reg = ((tmp_reg & 0x7fffffff) | (RA & 0x80000000));
|
||||
}
|
||||
RD = tmp_reg;
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(addkc,
|
||||
0x06,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA + RB + C_rd;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubkc,
|
||||
0x07,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RB + ~RA + C_rd;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(addi,
|
||||
0x08,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
CARRY = C_calc(RA, IMM, 0);
|
||||
RD = RA + IMM;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubi,
|
||||
0x09,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
CARRY = C_calc(IMM, ~RA, 1);
|
||||
RD = IMM + ~RA + 1;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(addic,
|
||||
0x0A,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
CARRY = C_calc(RA, IMM, C_rd);
|
||||
RD = RA + IMM + C_rd;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubic,
|
||||
0x0B,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
CARRY = C_calc(IMM, ~RA, C_rd);
|
||||
RD = IMM + ~RA + C_rd;
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(addik,
|
||||
0x0C,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA + IMM;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubik,
|
||||
0x0D,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = IMM + ~RA + 1;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(addikc,
|
||||
0x0E,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA + IMM + C_rd;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rsubikc,
|
||||
0x0F,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = IMM + ~RA + C_rd;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(mul,
|
||||
0x10,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA * RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(bsrl,
|
||||
0x11,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (uword)RA >> RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(bsra,
|
||||
0x11,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (word)RA >> RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(bsll,
|
||||
0x11,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (uword)RA << RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(idiv,
|
||||
0x12,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (word) RB / (word) RA;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(idivu,
|
||||
0x12,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (uword) RB / (uword) RA;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(muli,
|
||||
0x18,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA * IMM;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(bsrli,
|
||||
0x19,
|
||||
INST_TYPE_RD_RA_IMM5,
|
||||
RD = (uword)RA >> (IMM & 0x1F);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(bsrai,
|
||||
0x19,
|
||||
INST_TYPE_RD_RA_IMM5,
|
||||
RD = (word)RA >> (IMM & 0x1F);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(bslli,
|
||||
0x19,
|
||||
INST_TYPE_RD_RA_IMM5,
|
||||
RD = (uword)RA << (IMM & 0x1F);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(get,
|
||||
0x1b,
|
||||
INST_TYPE_RD_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(put,
|
||||
0x1b,
|
||||
INST_TYPE_R1_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(nget,
|
||||
0x1b,
|
||||
INST_TYPE_RD_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(nput,
|
||||
0x1b,
|
||||
INST_TYPE_R1_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(cget,
|
||||
0x1b,
|
||||
INST_TYPE_RD_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(cput,
|
||||
0x1b,
|
||||
INST_TYPE_R1_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(ncget,
|
||||
0x1b,
|
||||
INST_TYPE_RD_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(ncput,
|
||||
0x1b,
|
||||
INST_TYPE_R1_IMM12,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(or,
|
||||
0x20,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA | RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(and,
|
||||
0x21,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA & RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(xor,
|
||||
0x22,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA ^ RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(andn,
|
||||
0x23,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = RA & ~RB;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sra,
|
||||
0x24,
|
||||
INST_TYPE_RD_RA,
|
||||
CARRY = (RA & 0x1);
|
||||
RD = (int) (RA >> 1);
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(src,
|
||||
0x24,
|
||||
INST_TYPE_RD_RA,
|
||||
CARRY = (RA & 0x1);
|
||||
RD = ((((int) (RA >> 1)) & 0x7FFFFFFF) | (uword)(C_rd << 31));
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(srl,
|
||||
0x24,
|
||||
INST_TYPE_RD_RA,
|
||||
CARRY = (RA & 0x1);
|
||||
RD = (uword) ((RA >> 1) & 0x7FFFFFFF);
|
||||
C_wr(CARRY);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sext8,
|
||||
0x24,
|
||||
INST_TYPE_RD_RA,
|
||||
RD = MICROBLAZE_SEXT8(RA);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sext16,
|
||||
0x24,
|
||||
INST_TYPE_RD_RA,
|
||||
RD = MICROBLAZE_SEXT16(RA);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(wdc,
|
||||
0x24,
|
||||
INST_TYPE_RA_RB,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(wic,
|
||||
0x24,
|
||||
INST_TYPE_RA_RB,
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(mts,
|
||||
0x25,
|
||||
INST_TYPE_SA_RA,
|
||||
SA = RA;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(mfs,
|
||||
0x25,
|
||||
INST_TYPE_RD_SA,
|
||||
RD = SA;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(br,
|
||||
0x26,
|
||||
INST_TYPE_RB,
|
||||
PC += RB;
|
||||
BRANCH)
|
||||
|
||||
INSTRUCTION(brd,
|
||||
0x26,
|
||||
INST_TYPE_RB,
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(brld,
|
||||
0x26,
|
||||
INST_TYPE_RD_RB,
|
||||
RD = PC;
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bra,
|
||||
0x26,
|
||||
INST_TYPE_RB,
|
||||
PC = RB;
|
||||
BRANCH)
|
||||
|
||||
INSTRUCTION(brad,
|
||||
0x26,
|
||||
INST_TYPE_RB,
|
||||
PC = RB;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(brald,
|
||||
0x26,
|
||||
INST_TYPE_RD_RB,
|
||||
RD = PC;
|
||||
PC = RB;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(microblaze_brk,
|
||||
0x26,
|
||||
INST_TYPE_RD_RB,
|
||||
RD = PC;
|
||||
PC = RB;
|
||||
MSR = MSR | BIP_MASK;
|
||||
BRANCH)
|
||||
|
||||
INSTRUCTION(beq,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA == 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(beqd,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA == 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bne,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA != 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bned,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA != 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(blt,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA < 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bltd,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA < 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(ble,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA <= 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bled,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA <= 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bgt,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA > 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bgtd,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA > 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bge,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA >= 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bged,
|
||||
0x27,
|
||||
INST_TYPE_RA_RB,
|
||||
if (RA >= 0) {
|
||||
PC += RB;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(ori,
|
||||
0x28,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA | IMM;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(andi,
|
||||
0x29,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA & IMM;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(xori,
|
||||
0x2A,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA ^ IMM;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(andni,
|
||||
0x2B,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = RA & ~IMM;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(imm,
|
||||
0x2C,
|
||||
INST_TYPE_IMM,
|
||||
IMM_H = IMM_L;
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(rtsd,
|
||||
0x2D,
|
||||
INST_TYPE_RA_IMM,
|
||||
PC = RA + IMM;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(rtid,
|
||||
0x2D,
|
||||
INST_TYPE_RA_IMM,
|
||||
PC = RA + IMM;
|
||||
MSR = MSR | INTR_EN_MASK;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(rtbd,
|
||||
0x2D,
|
||||
INST_TYPE_RA_IMM,
|
||||
PC = RA + IMM;
|
||||
MSR = MSR & ~BIP_MASK;
|
||||
BRANCH;
|
||||
DELAY_SLOT;)
|
||||
|
||||
INSTRUCTION(bri,
|
||||
0x2E,
|
||||
INST_TYPE_IMM,
|
||||
PC += IMM;
|
||||
BRANCH)
|
||||
|
||||
INSTRUCTION(brid,
|
||||
0x2E,
|
||||
INST_TYPE_IMM,
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(brlid,
|
||||
0x2E,
|
||||
INST_TYPE_RD_IMM,
|
||||
RD = PC;
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(brai,
|
||||
0x2E,
|
||||
INST_TYPE_IMM,
|
||||
PC = IMM;
|
||||
BRANCH)
|
||||
|
||||
INSTRUCTION(braid,
|
||||
0x2E,
|
||||
INST_TYPE_IMM,
|
||||
PC = IMM;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bralid,
|
||||
0x2E,
|
||||
INST_TYPE_RD_IMM,
|
||||
RD = PC;
|
||||
PC = IMM;
|
||||
BRANCH;
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(brki,
|
||||
0x2E,
|
||||
INST_TYPE_RD_IMM,
|
||||
RD = PC;
|
||||
PC = IMM;
|
||||
MSR = MSR | BIP_MASK;
|
||||
BRANCH)
|
||||
|
||||
INSTRUCTION(beqi,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA == 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(beqid,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA == 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bnei,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA != 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bneid,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA != 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(blti,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA < 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bltid,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA < 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(blei,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA <= 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bleid,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA <= 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bgti,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA > 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bgtid,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA > 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(bgei,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA >= 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
})
|
||||
|
||||
INSTRUCTION(bgeid,
|
||||
0x2F,
|
||||
INST_TYPE_RA_IMM,
|
||||
if (RA >= 0) {
|
||||
PC += IMM;
|
||||
BRANCH;
|
||||
} else {
|
||||
PC += INST_SIZE;
|
||||
}
|
||||
DELAY_SLOT)
|
||||
|
||||
INSTRUCTION(lbu,
|
||||
0x30,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (MEM_RD_UBYTE(RA + RB));
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(lhu,
|
||||
0x31,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (MEM_RD_UHALF((RA + RB) & ~0x1));
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(lw,
|
||||
0x32,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
RD = (MEM_RD_WORD((RA + RB) & ~0x3));
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sb,
|
||||
0x34,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
MEM_WR_BYTE(RA + RB, RD);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sh,
|
||||
0x35,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
MEM_WR_HALF((RA + RB) & ~0x1, RD);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sw,
|
||||
0x36,
|
||||
INST_TYPE_RD_RA_RB,
|
||||
MEM_WR_WORD((RA + RB) & ~0x3, RD);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(lbui,
|
||||
0x38,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = (MEM_RD_UBYTE(RA + IMM));
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(lhui,
|
||||
0x39,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = (MEM_RD_UHALF((RA+IMM) & ~0x1));
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(lwi,
|
||||
0x3A,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
RD = (MEM_RD_WORD((RA+IMM) & ~0x3));
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(sbi,
|
||||
0x3C,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
MEM_WR_BYTE(RA + IMM, RD);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(shi,
|
||||
0x3D,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
MEM_WR_HALF((RA + IMM) & ~0x1, RD);
|
||||
PC += INST_SIZE)
|
||||
|
||||
INSTRUCTION(swi,
|
||||
0x3E,
|
||||
INST_TYPE_RD_RA_IMM,
|
||||
MEM_WR_WORD((RA + IMM) & ~0x3, RD);
|
||||
PC += INST_SIZE)
|
||||
64
sim/microblaze/sim-main.h
Normal file
64
sim/microblaze/sim-main.h
Normal file
@ -0,0 +1,64 @@
|
||||
#ifndef MICROBLAZE_SIM_MAIN
|
||||
#define MICROBLAZE_SIM_MAIN
|
||||
|
||||
/* Copyright 2009 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the Xilinx MicroBlaze simulator.
|
||||
|
||||
This library is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#include "microblaze.h"
|
||||
#include "sim-basics.h"
|
||||
typedef address_word sim_cia;
|
||||
#include "sim-base.h"
|
||||
|
||||
/* The machine state.
|
||||
This state is maintained in host byte order. The
|
||||
fetch/store register functions must translate between host
|
||||
byte order and the target processor byte order.
|
||||
Keeping this data in target byte order simplifies the register
|
||||
read/write functions. Keeping this data in native order improves
|
||||
the performance of the simulator. Simulation speed is deemed more
|
||||
important. */
|
||||
|
||||
/* The ordering of the microblaze_regset structure is matched in the
|
||||
gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */
|
||||
struct microblaze_regset
|
||||
{
|
||||
word regs[32]; /* primary registers */
|
||||
word spregs[2]; /* pc + msr */
|
||||
int cycles;
|
||||
int insts;
|
||||
int exception;
|
||||
unsigned long msize;
|
||||
unsigned char *memory;
|
||||
ubyte imm_enable;
|
||||
half imm_high;
|
||||
};
|
||||
|
||||
struct _sim_cpu {
|
||||
struct microblaze_regset microblaze_cpu;
|
||||
sim_cpu_base base;
|
||||
};
|
||||
|
||||
#define MAX_NR_PROCESSORS 1
|
||||
struct sim_state {
|
||||
sim_cpu cpu[MAX_NR_PROCESSORS];
|
||||
#define STATE_CPU(sd, n) (&(sd)->cpu[0])
|
||||
sim_state_base base;
|
||||
};
|
||||
#endif /* MICROBLAZE_SIM_MAIN */
|
||||
|
||||
95
sim/microblaze/sysdep.h
Normal file
95
sim/microblaze/sysdep.h
Normal file
@ -0,0 +1,95 @@
|
||||
/* System includes and definitions used by the Xilinx MicroBlaze simulator.
|
||||
Copyright (C) 1999 Free Software Foundation, Inc.
|
||||
Contributed by Cygnus Solutions.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#ifndef __SYSDEP_H
|
||||
#define __SYSDEP_H
|
||||
|
||||
#ifndef hosts_std_host_H
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <ctype.h>
|
||||
#include <string.h>
|
||||
#include <sys/file.h>
|
||||
#include "ansidecl.h"
|
||||
|
||||
#ifndef O_ACCMODE
|
||||
#define O_ACCMODE (O_RDONLY | O_WRONLY | O_RDWR)
|
||||
#endif
|
||||
#ifndef SEEK_SET
|
||||
#define SEEK_SET 0
|
||||
#endif
|
||||
#ifndef SEEK_CUR
|
||||
#define SEEK_CUR 1
|
||||
#endif
|
||||
#ifdef STDC_HEADERS
|
||||
#include <stdlib.h>
|
||||
/*#include <string.h>*/
|
||||
#else
|
||||
extern char *mktemp ();
|
||||
#ifndef memset
|
||||
extern PTR memset ();
|
||||
#endif
|
||||
|
||||
#ifndef DONTDECLARE_MALLOC
|
||||
extern PTR malloc ();
|
||||
extern PTR realloc ();
|
||||
#endif
|
||||
|
||||
#ifndef __GNUC__
|
||||
extern PTR memcpy ();
|
||||
#else
|
||||
/* char *memcpy (); */
|
||||
#endif
|
||||
|
||||
#ifdef __STDC__
|
||||
extern void free ();
|
||||
#else
|
||||
extern int free();
|
||||
#endif
|
||||
|
||||
#ifndef strchr
|
||||
extern char *strchr();
|
||||
#endif
|
||||
extern char *getenv();
|
||||
extern PTR memchr();
|
||||
extern char *strrchr();
|
||||
|
||||
extern char *strrchr();
|
||||
extern char *ctime();
|
||||
extern long atol();
|
||||
extern char *getenv();
|
||||
#endif /* STDC_HEADERS */
|
||||
|
||||
#ifndef BYTES_IN_PRINTF_INT
|
||||
#define BYTES_IN_PRINTF_INT 4
|
||||
#endif
|
||||
|
||||
#include "fopen-same.h"
|
||||
#define hosts_std_host_H
|
||||
#endif
|
||||
|
||||
#ifdef STDC_HEADERS
|
||||
#include <stddef.h>
|
||||
#endif /* STDC_HEADERS */
|
||||
|
||||
#endif /* __SYSDEP_H */
|
||||
Loading…
x
Reference in New Issue
Block a user