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2005-07-06 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add sse3. * config/tc-i386.h (CpuSSE3): Renamed from ... (CpuPNI): This. Defined as CpuSSE3. * doc/c-i386.texi: Document .sse3.
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@ -1,3 +1,12 @@
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2005-07-06 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add sse3.
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* config/tc-i386.h (CpuSSE3): Renamed from ...
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(CpuPNI): This. Defined as CpuSSE3.
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* doc/c-i386.texi: Document .sse3.
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2005-07-06 Jan Beulich <jbeulich@novell.com>
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* config/tc-ia64.c (nop): Use zero for L-unit pseudo-nop.
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@ -433,6 +433,7 @@ static const arch_entry cpu_arch[] = {
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{".mmx", CpuMMX },
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{".sse", CpuMMX|CpuMMX2|CpuSSE },
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{".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
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{".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
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{".3dnow", CpuMMX|Cpu3dnow },
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{".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
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{".padlock", CpuPadLock },
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@ -182,7 +182,8 @@ typedef struct
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#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x8000 /* 3dnow! support required */
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#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
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#define CpuPNI 0x20000 /* Prescott New Instructions required */
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#define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */
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#define CpuPNI CpuSSE3 /* Prescott New Instructions required */
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#define CpuPadLock 0x40000 /* VIA PadLock required */
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#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
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@ -701,7 +701,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
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@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
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@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
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@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.3dnow}
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@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow}
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@end multitable
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Apart from the warning, there are only two other effects on
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