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Add MIPS SB1 machine

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This commit is contained in:
Nick Clifton 2000-12-02 01:10:33 +00:00
parent 84ea6cf2c5
commit c6c98b3833
19 changed files with 100 additions and 42 deletions
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11
bfd/ChangeLog
View File

@ -36,6 +36,17 @@
(_bfd_mips_elf_final_write_processing): Add cases for
bfd_mach_mips5 and bfd_mach_mips64.
* bfd/aoutx.h (NAME(aout,machine_type)): Add a
bfd_mach_mips_sb1 case.
* bfd/archures.c (bfd_mach_mips_sb1): New constant.
* bfd/bfd-in2.h (bfd_mach_mips_sb1): New constant.
* bfd/cpu-mips.c (I_sb1): New constant.
(arch_info_struct): Add entry for bfd_mach_mips_sb1.
* bfd/elf32-mips.c (elf_mips_mach): Add case for
E_MIPS_MACH_SB1.
(_bfd_mips_elf_final_write_processing): Add case for
bfd_mach_mips_sb1.
2000-12-01 Joel Sherrill <joel@OARcorp.com>
* config.bfd (arm-*-rtems*, a29k-*rtems*): New targets.

1
bfd/aoutx.h
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@ -780,6 +780,7 @@ NAME(aout,machine_type) (arch, machine, unknown)
case bfd_mach_mips32_4k:
case bfd_mach_mips5:
case bfd_mach_mips64:
case bfd_mach_mips_sb1:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;

1
bfd/archures.c
View File

@ -135,6 +135,7 @@ DESCRIPTION
.#define bfd_mach_mips32_4k 3204113 {* 32, 04, octal 'K' *}
.#define bfd_mach_mips5 5
.#define bfd_mach_mips64 64
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 0
.#define bfd_mach_i386_i8086 1

1
bfd/bfd-in2.h
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@ -1403,6 +1403,7 @@ enum bfd_architecture
#define bfd_mach_mips32_4k 3204113 /* 32, 04, octal 'K' */
#define bfd_mach_mips5 5
#define bfd_mach_mips64 64
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1

4
bfd/cpu-mips.c
View File

@ -59,6 +59,7 @@ enum
I_mips32_4k,
I_mips5,
I_mips64,
I_sb1,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@ -83,7 +84,8 @@ static const bfd_arch_info_type arch_info_struct[] =
N (32, 32, bfd_mach_mips32, "mips:mips32", false, NN(I_mips32)),
N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, NN(I_mips32_4k)),
N (64, 64, bfd_mach_mips5, "mips:mips5", false, NN(I_mips5)),
N (64, 64, bfd_mach_mips64, "mips:mips64", false, 0),
N (64, 64, bfd_mach_mips64, "mips:mips64", false, NN(I_mips64)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", false, 0),
};
/* The default architecture is mips:3000, but with a machine number of

7
bfd/elf32-mips.c
View File

@ -1846,6 +1846,9 @@ elf_mips_mach (flags)
case E_MIPS_MACH_MIPS32_4K:
return bfd_mach_mips32_4k;
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
default:
switch (flags & EF_MIPS_ARCH)
{
@ -2369,6 +2372,10 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
case bfd_mach_mips64:
val = E_MIPS_ARCH_64;
break;
case bfd_mach_mips_sb1:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
}
elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);

72
bfd/po/bfd.pot
View File

@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2000-12-01 16:44-0800\n"
"POT-Creation-Date: 2000-12-01 17:03-0800\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@ -34,22 +34,22 @@ msgstr ""
msgid "%s: Bad relocation record imported: %d"
msgstr ""
#: aoutx.h:1258 aoutx.h:1672
#: aoutx.h:1259 aoutx.h:1673
#, c-format
msgid "%s: can not represent section `%s' in a.out object file format"
msgstr ""
#: aoutx.h:1642
#: aoutx.h:1643
#, c-format
msgid ""
"%s: can not represent section for symbol `%s' in a.out object file format"
msgstr ""
#: aoutx.h:1644
#: aoutx.h:1645
msgid "*unknown*"
msgstr ""
#: aoutx.h:3683
#: aoutx.h:3684
#, c-format
msgid "%s: relocateable link from %s to %s not supported"
msgstr ""
@ -660,7 +660,7 @@ msgstr ""
#. Ignore init flag - it may not be set, despite the flags field
#. containing valid data.
#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2652
#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2659
#, c-format
msgid "private flags = %lx:"
msgstr ""
@ -854,132 +854,132 @@ msgstr ""
msgid "Linking mips16 objects into %s format is not supported"
msgstr ""
#: elf32-mips.c:2539
#: elf32-mips.c:2546
#, c-format
msgid "%s: linking PIC files with non-PIC files"
msgstr ""
#: elf32-mips.c:2549
#: elf32-mips.c:2556
#, c-format
msgid "%s: linking abicalls files with non-abicalls files"
msgstr ""
#: elf32-mips.c:2578
#: elf32-mips.c:2585
#, c-format
msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"
msgstr ""
#: elf32-mips.c:2587
#: elf32-mips.c:2594
#, c-format
msgid "%s: ISA mismatch (%d) with previous modules (%d)"
msgstr ""
#: elf32-mips.c:2610
#: elf32-mips.c:2617
#, c-format
msgid "%s: ABI mismatch: linking %s module with previous %s modules"
msgstr ""
#: elf32-mips.c:2624 elf32-ppc.c:1481 elf64-sparc.c:2974
#: elf32-mips.c:2631 elf32-ppc.c:1481 elf64-sparc.c:2974
#, c-format
msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
msgstr ""
#: elf32-mips.c:2655
#: elf32-mips.c:2662
msgid " [abi=O32]"
msgstr ""
#: elf32-mips.c:2657
#: elf32-mips.c:2664
msgid " [abi=O64]"
msgstr ""
#: elf32-mips.c:2659
#: elf32-mips.c:2666
msgid " [abi=EABI32]"
msgstr ""
#: elf32-mips.c:2661
#: elf32-mips.c:2668
msgid " [abi=EABI64]"
msgstr ""
#: elf32-mips.c:2663
#: elf32-mips.c:2670
msgid " [abi unknown]"
msgstr ""
#: elf32-mips.c:2665
#: elf32-mips.c:2672
msgid " [abi=N32]"
msgstr ""
#: elf32-mips.c:2667
#: elf32-mips.c:2674
msgid " [abi=64]"
msgstr ""
#: elf32-mips.c:2669
#: elf32-mips.c:2676
msgid " [no abi set]"
msgstr ""
#: elf32-mips.c:2672
#: elf32-mips.c:2679
msgid " [mips1]"
msgstr ""
#: elf32-mips.c:2674
#: elf32-mips.c:2681
msgid " [mips2]"
msgstr ""
#: elf32-mips.c:2676
#: elf32-mips.c:2683
msgid " [mips3]"
msgstr ""
#: elf32-mips.c:2678
#: elf32-mips.c:2685
msgid " [mips4]"
msgstr ""
#: elf32-mips.c:2680
#: elf32-mips.c:2687
msgid " [mips5]"
msgstr ""
#: elf32-mips.c:2682
#: elf32-mips.c:2689
msgid " [mips32]"
msgstr ""
#: elf32-mips.c:2684
#: elf32-mips.c:2691
msgid " [mips64]"
msgstr ""
#: elf32-mips.c:2686
#: elf32-mips.c:2693
msgid " [unknown ISA]"
msgstr ""
#: elf32-mips.c:2689
#: elf32-mips.c:2696
msgid " [32bitmode]"
msgstr ""
#: elf32-mips.c:2691
#: elf32-mips.c:2698
msgid " [not 32bitmode]"
msgstr ""
#: elf32-mips.c:4340
#: elf32-mips.c:4347
msgid "static procedure (no name)"
msgstr ""
#: elf32-mips.c:4955 elf64-alpha.c:4378
#: elf32-mips.c:4962 elf64-alpha.c:4378
#, c-format
msgid "%s: illegal section name `%s'"
msgstr ""
#: elf32-mips.c:5519
#: elf32-mips.c:5526
msgid "not enough GOT space for local GOT entries"
msgstr ""
#: elf32-mips.c:6636
#: elf32-mips.c:6643
#, c-format
msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
msgstr ""
#: elf32-mips.c:7623
#: elf32-mips.c:7630
#, c-format
msgid "Malformed reloc detected for section %s"
msgstr ""
#: elf32-mips.c:7700
#: elf32-mips.c:7707
#, c-format
msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
msgstr ""

3
binutils/ChangeLog
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@ -7,6 +7,9 @@
* readelf.c (get_machine_flags): Add cases for E_MIPS_ARCH_5,
and E_MIPS_ARCH_64.
* readelf.c (get_machine_flags): Add case for
E_MIPS_MACH_SB1.
2000-11-30 Richard Earnshaw <rearnsha@arm.com>
* readelf.c (frame_display_row): Output 's' for DW_CFA_same_value.

1
binutils/readelf.c
View File

@ -1488,6 +1488,7 @@ get_machine_flags (e_flags, e_machine)
case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
case E_MIPS_MACH_MIPS32_4K: strcat (buf, ", mips32-4k"); break;
case E_MIPS_MACH_SB1: strcat (buf, ", sb1"); break;
default: strcat (buf, " UNKNOWN"); break;
}
break;

9
gas/ChangeLog
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@ -67,6 +67,15 @@
* doc/c-mips.texi: Likewise. Also update introduction
and ".set" usage information.
* config/tc-mips.c (md_show_usage): Add "sb1" to the
CPU list.
(mips_cpu_info_table): Add SB-1 entries.
* doc/c-mips.texi: Add "sb1" to the list of CPUs
known to the -mcpu option.
* doc/as.texinfo: Correct description of MIPS -mcpu
option, by copying some of the text from doc/c-mips.texi.
2000-12-01 Joel Sherrill <joel@OARcorp.com>
* configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*):

7
gas/config/tc-mips.c
View File

@ -9243,6 +9243,7 @@ MIPS options:\n\
show (stream, "8000", &column, &first);
show (stream, "10000", &column, &first);
show (stream, "mips32-4k", &column, &first);
show (stream, "sb-1", &column, &first);
fputc ('\n', stream);
fprintf (stream, _("\
@ -12048,6 +12049,12 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_4K, },
{ "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, },
/* SiByte SB-1 CPU */
{ "SB-1", 0, ISA_MIPS64, CPU_SB1, },
{ "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
{ "sb1", 0, ISA_MIPS64, CPU_SB1, },
{ "sb1250", 0, ISA_MIPS64, CPU_SB1, },
/* End marker. */
{ NULL, 0, 0, 0, },
};

5
gas/doc/as.texinfo
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@ -689,8 +689,9 @@ instructions around accesses to the @samp{HI} and @samp{LO} registers.
@samp{-no-m4650} turns off this option.
@item -mcpu=@var{CPU}
Generate code for a particular MIPS cpu. This has little effect on the
assembler, but it is passed by @code{@value{GCC}}.
Generate code for a particular MIPS cpu. It is exactly equivalent to
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
understood.
@cindex emulation
@item --emulation=@var{name}

3
gas/doc/c-mips.texi
View File

@ -149,7 +149,8 @@ rm5721,
rm7000,
8000,
10000,
mips32-4k
mips32-4k,
sb1
@end quotation

2
include/elf/ChangeLog
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@ -6,6 +6,8 @@
* mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
* mips.h (E_MIPS_MACH_SB1): New constant.
2000-11-30 Jan Hubicka <jh@suse.cz>
* common.h (EM_X86_64): New macro.

1
include/elf/mips.h
View File

@ -163,6 +163,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_MIPS32_4K 0x00890000
#define E_MIPS_MACH_SB1 0x008a0000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these

2
include/opcode/ChangeLog
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@ -28,6 +28,8 @@
* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
definitions.
* mips.h (CPU_SB1): New constant.
2000-10-20 Jakub Jelinek <jakub@redhat.com>
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.

5
include/opcode/mips.h
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@ -359,9 +359,10 @@ struct mips_opcode
#define CPU_R10000 10000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */
#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */
#define CPU_MIPS5 5
#define CPU_MIPS64 64
#define CPU_SB1 12310201 /* octal 'SB', 01. */
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
@ -369,7 +370,7 @@ struct mips_opcode
to test, or zero if no CPU specific ISA test is desired.
The gp32 arg is set when you need to force 32-bit register usage on
a machine with 64-bit registers; see the documentation under -mgp32
in the MIPS gas docs. */
in the MIPS gas docs. */
#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
((((insn)->membership & isa) != 0 \

3
opcodes/ChangeLog
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@ -29,6 +29,9 @@
bfd_mach_mips5 and bfd_mach_mips64.
* mips-opc.c (I64): New definitions.
* mips-dis.c (set_mips_isa_type): Add case for
bfd_mach_mips_sb1.
2000-11-28 Hans-Peter Nilsson <hp@bitrange.com>
* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.

4
opcodes/mips-dis.c
View File

@ -371,6 +371,10 @@ set_mips_isa_type (mach, isa, cputype)
target_processor = CPU_MIPS64;
mips_isa = ISA_MIPS64;
break;
case bfd_mach_mips_sb1:
target_processor = CPU_SB1;
mips_isa = ISA_MIPS64;
break;
default:
target_processor = CPU_R3000;
mips_isa = ISA_MIPS3;