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[AArch64] Add ARMv8.3 PACGA instruction
Add support for the ARMv8.3 PACGA instruction. include/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP. opcodes/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add pacga. (AARCH64_OPERANDS): Add Rm_SP. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/pac.s: Add pacga. * testsuite/gas/aarch64/pac.d: Add pacga.
This commit is contained in:
Szabolcs Nagy
parent
a2cfc830e7
commit
c84364ece4
@ -1,3 +1,10 @@
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
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(parse_operands): Likewise.
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* testsuite/gas/aarch64/pac.s: Add pacga.
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* testsuite/gas/aarch64/pac.d: Add pacga.
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* testsuite/gas/aarch64/pac.s: New.
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@ -4983,6 +4983,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
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case AARCH64_OPND_Rt_SYS:
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_Rm_SP:
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case AARCH64_OPND_Fd:
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case AARCH64_OPND_Fn:
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case AARCH64_OPND_Fm:
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@ -5314,6 +5315,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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case AARCH64_OPND_Rm_SP:
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po_int_reg_or_fail (REG_TYPE_R_SP);
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break;
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@ -32,3 +32,5 @@ Disassembly of section \.text:
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5c: dac13fe5 autdzb x5
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60: dac143e5 xpaci x5
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64: dac147e5 xpacd x5
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68: 9ac33041 pacga x1, x2, x3
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6c: 9adf3041 pacga x1, x2, sp
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@ -32,3 +32,6 @@
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xpaci x5
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xpacd x5
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pacga x1, x2, x3
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pacga x1, x2, sp
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@ -1,3 +1,7 @@
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
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@ -140,6 +140,7 @@ enum aarch64_opnd
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AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
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AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
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AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
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AARCH64_OPND_PAIRREG, /* Paired register operand. */
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AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
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AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
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@ -1,3 +1,12 @@
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-tbl.h (arch64_opcode_table): Add pacga.
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(AARCH64_OPERANDS): Add Rm_SP.
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* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -35,6 +35,7 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
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{AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
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{AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
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{AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"},
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{AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
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{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
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{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
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@ -208,48 +209,48 @@ const struct aarch64_operand aarch64_operands[] =
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static const unsigned op_enum_table [] =
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{
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0,
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846,
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847,
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848,
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851,
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849,
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852,
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853,
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854,
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855,
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849,
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850,
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856,
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850,
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851,
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857,
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879,
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858,
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880,
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881,
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884,
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882,
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885,
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886,
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887,
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888,
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882,
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883,
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889,
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883,
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884,
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890,
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933,
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891,
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934,
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935,
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936,
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937,
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12,
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627,
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628,
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1128,
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1130,
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1132,
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940,
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1131,
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1129,
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1131,
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1133,
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941,
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1132,
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1130,
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311,
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615,
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626,
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625,
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938,
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939,
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622,
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619,
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611,
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@ -259,34 +260,34 @@ static const unsigned op_enum_table [] =
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621,
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623,
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624,
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948,
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949,
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643,
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646,
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649,
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644,
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647,
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790,
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791,
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171,
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172,
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173,
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174,
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507,
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731,
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732,
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380,
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382,
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404,
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406,
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1193,
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1198,
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1191,
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1190,
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1194,
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1201,
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1203,
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1199,
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1192,
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1191,
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1195,
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1202,
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1204,
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1200,
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1206,
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1205,
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1201,
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1207,
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1206,
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};
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/* Given the opcode enumerator OP, return the pointer to the corresponding
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@ -2989,6 +2989,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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case AARCH64_OPND_Rd_SP:
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case AARCH64_OPND_Rn_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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case AARCH64_OPND_Rm_SP:
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assert (opnd->qualifier == AARCH64_OPND_QLF_W
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|| opnd->qualifier == AARCH64_OPND_QLF_WSP
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|| opnd->qualifier == AARCH64_OPND_QLF_X
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@ -2694,6 +2694,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
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CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS),
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CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
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V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
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/* CRC instructions. */
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_CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
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_CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
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@ -3987,6 +3988,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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"an integer or stack pointer register") \
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Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
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"an integer or stack pointer register") \
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Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \
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"an integer or stack pointer register") \
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X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
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"the second reg of a pair") \
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Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
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