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gas/ChangeLog

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* config/tc-i386.c (process_suffix): Remove intel mode movsx and
	movzx fudges.
	(md_assemble): Instead, zap the suffix here.

include/opcode/ChangeLog
	* i386.h: Remove IgnoreSize from movsx and movzx.
This commit is contained in:
Alan Modra 2002-07-08 10:03:11 +00:00
parent aecc8f8acd
commit cd61ebfe13
4 changed files with 27 additions and 21 deletions
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6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2002-07-08 Alan Modra <amodra@bigpond.net.au>
* config/tc-i386.c (process_suffix): Remove intel mode movsx and
movzx fudges.
(md_assemble): Instead, zap the suffix here.
2002-07-03 Nick Clifton <nickc@cambridge.redhat.com>
* NEWS: Remove next release number until the release is actually

22
gas/config/tc-i386.c
View File

@ -1326,12 +1326,20 @@ md_assemble (line)
if (!match_template ())
return;
if (intel_syntax)
{
/* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
if (SYSV386_COMPAT
&& intel_syntax
&& (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
i.tm.base_opcode ^= FloatR;
/* Zap movzx and movsx suffix. The suffix may have been set from
"word ptr" or "byte ptr" on the source operand, but we'll use
the suffix later to choose the destination register. */
if ((i.tm.base_opcode & ~9) == 0x0fb6)
i.suffix = 0;
}
if (i.tm.opcode_modifier & FWait)
if (!add_prefix (FWAIT_OPCODE))
return;
@ -2218,18 +2226,6 @@ process_suffix ()
return 0;
}
/* For movzx and movsx, need to check the register type. */
if (intel_syntax
&& (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
&& i.suffix == BYTE_MNEM_SUFFIX)
{
unsigned int prefix = DATA_PREFIX_OPCODE;
if ((i.op[1].regs->reg_type & Reg16) != 0)
if (!add_prefix (prefix))
return 0;
}
if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
{
/* It's not a byte, select word/dword operation. */

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2002-07-08 Alan Modra <amodra@bigpond.net.au>
* i386.h: Remove IgnoreSize from movsx and movzx.
2002-06-08 Alan Modra <amodra@bigpond.net.au>
* a29k.h: Replace CONST with const.

8
include/opcode/i386.h
View File

@ -121,9 +121,9 @@ static const template i386_optab[] = {
{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
/* Intel Syntax next 5 insns */
{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} },
{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} },
{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
/* Move with zero extend. */
@ -135,11 +135,11 @@ static const template i386_optab[] = {
{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
/* Intel Syntax next 4 insns */
{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} },
/* These instructions are not particulary usefull, since the zero extend
32->64 is implicit, but we can encode them. */
{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} },
{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
/* Push instructions. */
{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },