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Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com>

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* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
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Martin Hunt 1996-08-09 20:25:12 +00:00
parent 611f046fe2
commit cff827d7df
2 changed files with 8 additions and 2 deletions
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8
opcodes/ChangeLog
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@ -1,3 +1,9 @@
start-sanitize-d10v
Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
end-sanitize-d10v
Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de>
* makefile.vms: Update for alpha-opc changes.
@ -10,7 +16,7 @@ Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com>
start-sanitize-d10v
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
* d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
end-sanitize-d10v

2
opcodes/d10v-opc.c
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@ -220,7 +220,7 @@ const struct d10v_opcode d10v_opcodes[] = {
{ "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } },
{ "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } },
{ "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } },
{ "mv", SHORT_2, 1, IU, PAR, 0x4000, 0x7e01, { RDST, RSRC } },
{ "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } },
{ "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } },
{ "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } },
{ "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } },