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https://github.com/darlinghq/darling-gdb.git
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2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and CpuAmdFam10. (smallest_imm_type): Remove Cpu086. (i386_target_format): Likewise. * config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10. Update CpuXXX.
This commit is contained in:
H.J. Lu
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9691cba8cb
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@ -1,3 +1,13 @@
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2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
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CpuAmdFam10.
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(smallest_imm_type): Remove Cpu086.
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(i386_target_format): Likewise.
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* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
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Update CpuXXX.
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2006-07-13 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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Michael Meissner <michael.meissner@amd.com>
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@ -434,67 +434,67 @@ const relax_typeS md_relax_table[] =
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static const arch_entry cpu_arch[] =
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{
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{"generic32", PROCESSOR_GENERIC32,
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Cpu086|Cpu186|Cpu286|Cpu386},
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Cpu186|Cpu286|Cpu386},
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{"generic64", PROCESSOR_GENERIC64,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2},
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{"i8086", PROCESSOR_UNKNOWN,
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Cpu086},
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0},
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{"i186", PROCESSOR_UNKNOWN,
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Cpu086|Cpu186},
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Cpu186},
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{"i286", PROCESSOR_UNKNOWN,
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Cpu086|Cpu186|Cpu286},
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Cpu186|Cpu286},
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{"i386", PROCESSOR_GENERIC32,
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Cpu086|Cpu186|Cpu286|Cpu386},
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Cpu186|Cpu286|Cpu386},
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{"i486", PROCESSOR_I486,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486},
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Cpu186|Cpu286|Cpu386|Cpu486},
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{"i586", PROCESSOR_PENTIUM,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
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{"i686", PROCESSOR_PENTIUMPRO,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
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{"pentium", PROCESSOR_PENTIUM,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
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{"pentiumpro",PROCESSOR_PENTIUMPRO,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
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{"pentiumii", PROCESSOR_PENTIUMPRO,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
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{"pentiumiii",PROCESSOR_PENTIUMPRO,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2
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|CpuSSE},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
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{"pentium4", PROCESSOR_PENTIUM4,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2},
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{"prescott", PROCESSOR_NOCONA,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{"nocona", PROCESSOR_NOCONA,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{"yonah", PROCESSOR_YONAH,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
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{"merom", PROCESSOR_MEROM,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
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|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
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{"k6", PROCESSOR_K6,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
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{"k6_2", PROCESSOR_K6,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
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{"athlon", PROCESSOR_ATHLON,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
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|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
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{"sledgehammer", PROCESSOR_K8,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
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|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
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{"opteron", PROCESSOR_K8,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
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|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
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{"k8", PROCESSOR_K8,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
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|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
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{"amdfam10", PROCESSOR_AMDFAM10,
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Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
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|CpuSledgehammer|CpuAmdFam10|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM},
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Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
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|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
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|CpuABM},
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{".mmx", PROCESSOR_UNKNOWN,
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CpuMMX},
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{".sse", PROCESSOR_UNKNOWN,
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@ -936,7 +936,7 @@ static int
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smallest_imm_type (num)
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offsetT num;
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{
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if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
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if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
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{
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/* This code is disabled on the 486 because all the Imm1 forms
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in the opcode table are slower on the i486. They're the
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@ -5942,11 +5942,11 @@ i386_target_format ()
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{
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set_code_flag (CODE_64BIT);
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if (cpu_arch_isa_flags == 0)
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cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
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cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
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|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
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|CpuSSE|CpuSSE2;
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if (cpu_arch_tune_flags == 0)
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cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
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cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
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|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
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|CpuSSE|CpuSSE2;
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}
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@ -5954,9 +5954,9 @@ i386_target_format ()
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{
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set_code_flag (CODE_32BIT);
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if (cpu_arch_isa_flags == 0)
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cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386;
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cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
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if (cpu_arch_tune_flags == 0)
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cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386;
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cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
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}
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else
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as_fatal (_("Unknown architecture"));
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@ -162,41 +162,38 @@ typedef struct
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/* cpu feature flags */
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unsigned int cpu_flags;
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#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
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#define Cpu186 0x2 /* i186 or better required */
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#define Cpu286 0x4 /* i286 or better required */
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#define Cpu386 0x8 /* i386 or better required */
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#define Cpu486 0x10 /* i486 or better required */
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#define Cpu586 0x20 /* i585 or better required */
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#define Cpu686 0x40 /* i686 or better required */
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#define CpuP4 0x80 /* Pentium4 or better required */
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#define CpuK6 0x100 /* AMD K6 or better required*/
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#define CpuAthlon 0x200 /* AMD Athlon or better required*/
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#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
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#define CpuMMX 0x800 /* MMX support required */
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#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */
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#define CpuSSE 0x2000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x8000 /* 3dnow! support required */
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#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
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#define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */
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#define Cpu186 0x1 /* i186 or better required */
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#define Cpu286 0x2 /* i286 or better required */
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#define Cpu386 0x4 /* i386 or better required */
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#define Cpu486 0x8 /* i486 or better required */
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#define Cpu586 0x10 /* i585 or better required */
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#define Cpu686 0x20 /* i686 or better required */
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#define CpuP4 0x40 /* Pentium4 or better required */
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#define CpuK6 0x80 /* AMD K6 or better required*/
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#define CpuSledgehammer 0x100 /* Sledgehammer or better required */
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#define CpuMMX 0x200 /* MMX support required */
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#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
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#define CpuSSE 0x800 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x2000 /* 3dnow! support required */
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#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */
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#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */
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#define CpuPNI CpuSSE3 /* Prescott New Instructions required */
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#define CpuPadLock 0x40000 /* VIA PadLock required */
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#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
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#define CpuVMX 0x100000 /* VMX Instructions required */
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#define CpuMNI 0x200000 /* Merom New Instructions required */
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#define CpuSSE4a 0x400000 /* SSE4a New Instuctions required */
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#define CpuABM 0x800000 /* ABM New Instructions required */
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#define CpuAmdFam10 0x1000000 /* AmdFam10 New instructions required */
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#define CpuPadLock 0x10000 /* VIA PadLock required */
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#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
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#define CpuVMX 0x40000 /* VMX Instructions required */
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#define CpuMNI 0x80000 /* Merom New Instructions required */
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#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
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#define CpuABM 0x200000 /* ABM New Instructions required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuAmdFam10|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI|CpuABM|CpuSSE4a)
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuMNI|CpuABM|CpuSSE4a)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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