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* config/tc-mips.c (hilo_interlocks): Remove mips_3900.
(append_insn): Account for the tx39's multiply behavior. * mips.h (INSN_MULT): Added. * mips-opc.c (IS_M): Added.
This commit is contained in:
Gavin Romig-Koch
parent
fda83b6795
commit
d3b42ce1c7
@ -1,3 +1,8 @@
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Tue Oct 27 08:56:44 1998 Gavin Romig-Koch <gavin@cygnus.com>
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* config/tc-mips.c (hilo_interlocks): Remove mips_3900.
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(append_insn): Account for the tx39's multiply behavior.
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1998-10-26 Michael Meissner <meissner@cygnus.com>
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* config/tc-m32r.c (assemble_two_insns): Rename assemble_two_insns
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@ -1,3 +1,11 @@
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Tue Oct 27 08:57:59 1998 Gavin Romig-Koch <gavin@cygnus.com>
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* mips.h (INSN_MULT): Added.
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Tue Oct 20 11:31:34 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
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* i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
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Mon Oct 19 12:50:00 1998 Doug Evans <devans@seba.cygnus.com>
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* cgen.h (CGEN_INSN_INT): New typedef.
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@ -47,7 +47,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
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breakpoint instruction are not defined; Kane says the breakpoint
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code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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only use ten bits).
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only use ten bits). An optional two-operand form of break/sdbbp
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allows the lower ten bits to be set too.
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The syscall instruction uses SYSCALL.
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@ -65,6 +66,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_SH_BCC 18
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#define OP_MASK_CODE 0x3ff
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#define OP_SH_CODE 16
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#define OP_MASK_CODE2 0x3ff
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#define OP_SH_CODE2 6
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#define OP_MASK_RT 0x1f
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#define OP_SH_RT 16
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#define OP_MASK_FT 0x1f
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@ -121,15 +124,33 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_MASK_MMI 0x3f
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#define OP_SH_MMISUB 6
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#define OP_MASK_MMISUB 0x1f
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/* start-sanitize-vr5400 */
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
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#define OP_SH_PERFREG 1
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/* start-sanitize-cygnus */
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#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
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but 0x8-0xf don't select bytes. */
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#define OP_SH_VECBYTE 22
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
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#define OP_SH_VECALIGN 21
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/* end-sanitize-vr5400 */
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/* end-sanitize-cygnus */
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/* start-sanitize-r5900 */
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#define OP_SH_VADDI 6
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#define OP_MASK_VADDI 0x1f
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#define OP_SH_VUTREG 16
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#define OP_MASK_VUTREG 0x1f
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#define OP_SH_VUSREG 11
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#define OP_MASK_VUSREG 0x1f
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#define OP_SH_VUDREG 6
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#define OP_MASK_VUDREG 0x1f
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#define OP_SH_VUFSF 21
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#define OP_MASK_VUFSF 0x3
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#define OP_SH_VUFTF 23
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#define OP_MASK_VUFTF 0x3
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#define OP_SH_VUDEST 21
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#define OP_MASK_VUDEST 0xf
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#define OP_SH_VUCALLMS 6
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#define OP_MASK_VUCALLMS 0x7fff
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/* end-sanitize-r5900 */
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/* This structure holds information for a particular instruction. */
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@ -141,9 +162,7 @@ struct mips_opcode
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const char *args;
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/* The basic opcode for the instruction. When assembling, this
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opcode is modified by the arguments to produce the actual opcode
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that is used. If pinfo is INSN_MACRO, then this is instead the
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ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
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etc.). */
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that is used. If pinfo is INSN_MACRO, then this is 0. */
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unsigned long match;
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/* If pinfo is not INSN_MACRO, then this is a bit mask for the
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relevant portions of the opcode when disassembling. If the
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@ -156,7 +175,7 @@ struct mips_opcode
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information. */
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unsigned long pinfo;
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/* A collection of bits describing the instruction sets of which this
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instruction is a member. */
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instruction or macro is a member. */
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unsigned long membership;
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};
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@ -178,11 +197,12 @@ struct mips_opcode
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"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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"j" 16 bit signed immediate (OP_*_DELTA)
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"k" 5 bit cache opcode in target register position (OP_*_CACHE)
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start-sanitize-vr5400
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start-sanitize-cygnus
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also vr5400 vector ops immediate operand
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end-sanitize-vr5400
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end-sanitize-cygnus
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"o" 16 bit signed offset (OP_*_DELTA)
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"p" 16 bit PC relative branch target address (OP_*_DELTA)
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"q" 10 bit extra breakpoint code (OP_*_CODE2)
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"r" 5 bit same register used as both source and target (OP_*_RS)
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"s" 5 bit source register specifier (OP_*_RS)
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"t" 5 bit target register (OP_*_RT)
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@ -207,12 +227,12 @@ end-sanitize-vr5400
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Coprocessor instructions:
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"E" 5 bit target register (OP_*_RT)
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"G" 5 bit destination register (OP_*_RD)
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start-sanitize-vr5400
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"P" 5 bit performance-monitor register (OP_*_PERFREG)
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start-sanitize-cygnus
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"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
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"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
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see also "k" above
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end-sanitize-vr5400
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end-sanitize-cygnus
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Macro instructions:
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"A" General 32 bit expression
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@ -225,17 +245,17 @@ end-sanitize-vr5400
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Other:
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"()" parens surrounding optional value
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"," separates operands
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start-sanitize-vr5400
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start-sanitize-cygnus
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"[]" brackets around index for vector-op scalar operand specifier (vr5400)
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end-sanitize-vr5400
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end-sanitize-cygnus
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Characters used so far, for quick reference when adding more:
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start-sanitize-vr5400
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start-sanitize-cygnus
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"Pe%[]" plus...
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end-sanitize-vr5400
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end-sanitize-cygnus
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"<>(),"
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"ABCDEFGILMNSTRVW"
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"abcdfhijkloprstuvwxz"
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"abcdfhijklopqrstuvwxz"
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*/
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/* These are the bits which may be set in the pinfo field of an
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@ -301,8 +321,8 @@ end-sanitize-vr5400
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#define FP_S 0x10000000
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/* Instruction uses double precision floating point. */
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#define FP_D 0x20000000
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/* As yet unused bits: 0x40000000 */
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/* Instruction is part of the tx39's integer multiply family. */
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#define INSN_MULT 0x40000000
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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@ -335,10 +355,14 @@ end-sanitize-vr5400
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#define INSN_4100 0x00000040
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/* Toshiba R3900 instruction. */
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#define INSN_3900 0x00000080
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/* start-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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/* NEC VR4320 instruction. */
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#define INSN_4320 0x00002000
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/* end-sanitize-vr4320 */
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/* start-sanitize-cygnus */
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/* NEC VR5400 instruction. */
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#define INSN_5400 0x00001000
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/* end-sanitize-vr5400 */
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/* end-sanitize-cygnus */
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/* start-sanitize-r5900 */
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/* Toshiba R5900 instruction */
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#define INSN_5900 0x00000100
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@ -1,3 +1,7 @@
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Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com>
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* mips-opc.c (IS_M): Added.
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start-sanitize-r5900
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Fri Oct 23 12:06:00 EDT 1998 Frank Ch. Eigler <fche@cygnus.com>
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@ -70,6 +70,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define RD_HILO RD_HI|RD_LO
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#define MOD_HILO WR_HILO|RD_HILO
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#define IS_M INSN_MULT
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#define I1 INSN_ISA1
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#define I2 INSN_ISA2
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@ -710,15 +711,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 },
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/* end-sanitize-r5900 */
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{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
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{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, G1 },
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{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1 },
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{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1 },
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{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
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/* start-sanitize-r5900 */
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{"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
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{"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
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/* end-sanitize-r5900 */
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{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
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{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, G1 },
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{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1 },
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{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1},
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{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
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/* start-sanitize-r5900 */
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{"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
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{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
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@ -882,14 +883,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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/* end-sanitize-cygnus */
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{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
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{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1},
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{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1},
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{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
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/* start-sanitize-r5900 */
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{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5},
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{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
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/* end-sanitize-r5900 */
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{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
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{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1},
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{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1},
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{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
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/* start-sanitize-r5900 */
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{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5},
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{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
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