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Fix normal operation for h8300-coff target
This commit is contained in:
Nick Clifton
parent
ece01a639d
commit
d4e2de6bc2
@ -1,3 +1,15 @@
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2003-10-17 Shrinivas Atre <shrinivasa@KPITCummins.com>
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* coff-h8300.c (funcvec_hash_newfunc): Handle normal mode.
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(h8300_reloc16_extra_cases): Likewise.
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(h8300_bfd_link_add_symbols): Likewise.
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2003-10-17 Dhananjay Deshpande <dhananjayd@kpitcummins.com>
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* cpu-h8300.c (h8300sxn_info_struct): Correct address size.
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(h8300sn_info_struct): Likewise.
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(h8300hn_info_struct): Likewise.
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2003-10-16 Pavel Roskin <proski@gnu.org>
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* peXXigen.c (_bfd_XXi_swap_aouthdr_out): Don't calculate image size
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@ -154,13 +154,20 @@ funcvec_hash_newfunc (struct bfd_hash_entry *entry,
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/* Bump the offset at which we store entries in the function
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vector. We'd like to bump up the size of the vectors section,
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but it's not easily available here. */
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if (bfd_get_mach (table->abfd) == bfd_mach_h8300)
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table->offset += 2;
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else if (bfd_get_mach (table->abfd) == bfd_mach_h8300h
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|| bfd_get_mach (table->abfd) == bfd_mach_h8300s)
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table->offset += 4;
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else
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return NULL;
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switch (bfd_get_mach (table->abfd))
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{
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case bfd_mach_h8300:
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case bfd_mach_h8300hn:
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case bfd_mach_h8300sn:
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table->offset += 2;
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break;
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case bfd_mach_h8300h:
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case bfd_mach_h8300s:
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table->offset += 4;
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break;
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default:
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return NULL;
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}
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/* Everything went OK. */
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return (struct bfd_hash_entry *) ret;
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@ -1096,6 +1103,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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if (symbol->flags & BSF_LOCAL)
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{
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char *new_name = bfd_malloc ((bfd_size_type) strlen (name) + 9);
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if (new_name == NULL)
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abort ();
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@ -1124,21 +1132,28 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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src_address++;
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/* Now create an entry in the function vector itself. */
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if (bfd_get_mach (input_section->owner) == bfd_mach_h8300)
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bfd_put_16 (abfd,
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bfd_coff_reloc16_get_value (reloc,
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link_info,
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input_section),
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vectors_sec->contents + h->offset);
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else if (bfd_get_mach (input_section->owner) == bfd_mach_h8300h
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|| bfd_get_mach (input_section->owner) == bfd_mach_h8300s)
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bfd_put_32 (abfd,
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bfd_coff_reloc16_get_value (reloc,
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link_info,
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input_section),
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vectors_sec->contents + h->offset);
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else
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abort ();
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switch (bfd_get_mach (input_section->owner))
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{
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case bfd_mach_h8300:
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case bfd_mach_h8300hn:
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case bfd_mach_h8300sn:
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bfd_put_16 (abfd,
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bfd_coff_reloc16_get_value (reloc,
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link_info,
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input_section),
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vectors_sec->contents + h->offset);
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break;
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case bfd_mach_h8300h:
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case bfd_mach_h8300s:
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bfd_put_32 (abfd,
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bfd_coff_reloc16_get_value (reloc,
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link_info,
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input_section),
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vectors_sec->contents + h->offset);
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break;
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default:
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abort ();
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}
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/* Gross. We've already written the contents of the vector section
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before we get here... So we write it again with the new data. */
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@ -1304,11 +1319,20 @@ h8300_bfd_link_add_symbols (bfd *abfd, struct bfd_link_info *info)
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/* Bump the size of the vectors section. Each vector
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takes 2 bytes on the h8300 and 4 bytes on the h8300h. */
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if (bfd_get_mach (abfd) == bfd_mach_h8300)
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htab->vectors_sec->_raw_size += 2;
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else if (bfd_get_mach (abfd) == bfd_mach_h8300h
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|| bfd_get_mach (abfd) == bfd_mach_h8300s)
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htab->vectors_sec->_raw_size += 4;
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switch (bfd_get_mach (abfd))
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{
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case bfd_mach_h8300:
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case bfd_mach_h8300hn:
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case bfd_mach_h8300sn:
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htab->vectors_sec->_raw_size += 2;
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break;
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case bfd_mach_h8300h:
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case bfd_mach_h8300s:
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htab->vectors_sec->_raw_size += 4;
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break;
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default:
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abort ();
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}
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}
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}
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}
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@ -23,11 +23,6 @@
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#include "sysdep.h"
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#include "libbfd.h"
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static bfd_boolean h8300_scan
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(const struct bfd_arch_info *, const char *);
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static const bfd_arch_info_type * compatible
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(const bfd_arch_info_type *, const bfd_arch_info_type *);
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static bfd_boolean
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h8300_scan (const struct bfd_arch_info *info, const char *string)
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{
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@ -111,7 +106,7 @@ compatible (const bfd_arch_info_type *in, const bfd_arch_info_type *out)
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static const bfd_arch_info_type h8300sxn_info_struct =
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{
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32, /* 32 bits in a word */
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32, /* 32 bits in an address */
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16, /* 16 bits in an address */
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8, /* 8 bits in a byte */
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bfd_arch_h8300,
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bfd_mach_h8300sxn,
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@ -143,7 +138,7 @@ static const bfd_arch_info_type h8300sx_info_struct =
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static const bfd_arch_info_type h8300sn_info_struct =
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{
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32, /* 32 bits in a word. */
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32, /* 32 bits in an address. */
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16, /* 16 bits in an address. */
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8, /* 8 bits in a byte. */
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bfd_arch_h8300,
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bfd_mach_h8300sn,
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@ -156,11 +151,10 @@ static const bfd_arch_info_type h8300sn_info_struct =
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&h8300sx_info_struct
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};
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static const bfd_arch_info_type h8300hn_info_struct =
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{
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32, /* 32 bits in a word. */
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32, /* 32 bits in an address. */
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16, /* 16 bits in an address. */
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8, /* 8 bits in a byte. */
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bfd_arch_h8300,
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bfd_mach_h8300hn,
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@ -1,3 +1,10 @@
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2003-10-17 Shrinivas Atre <shrinivasa@KPITCummins.com>
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* config/tc-h8300.c (PSIZE): Correct for Normal mode.
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(get_operand): Accept both 16 bit 32 bit registers as pointer
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registers, when operating in Normal mode.
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(fix_operand_size): Make default address size 16 for Normal mode.
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2003-10-17 Ian Lance Taylor <ian@wasabisystems.com>
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* config/tc-arm.c (do_iwmmxt_byte_addr): Reject control
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@ -58,7 +58,7 @@ int Smode;
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int Nmode;
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int SXmode;
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#define PSIZE (Hmode ? L_32 : L_16)
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#define PSIZE (Hmode && !Nmode ? L_32 : L_16)
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int bsize = L_8; /* Default branch displacement. */
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@ -689,7 +689,7 @@ get_operand (ptr, op, direction)
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*ptr = parse_exp (src + 1, op);
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if (op->exp.X_add_number >= 0x100)
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{
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int divisor;
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int divisor = 1;
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op->mode = VECIND;
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/* FIXME : 2? or 4? */
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@ -718,7 +718,9 @@ get_operand (ptr, op, direction)
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return;
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}
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if ((mode & SIZE) != PSIZE)
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if (((mode & SIZE) != PSIZE)
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/* For Normal mode accept 16 bit and 32 bit pointer registers. */
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&& (!Nmode || ((mode & SIZE) != L_32)))
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as_bad (_("Wrong size pointer register for architecture."));
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op->mode = src[0] == '-' ? RDPREDEC : RDPREINC;
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@ -828,7 +830,9 @@ get_operand (ptr, op, direction)
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src += len;
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if (*src == '+' || *src == '-')
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{
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if ((mode & SIZE) != PSIZE)
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if (((mode & SIZE) != PSIZE)
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/* For Normal mode accept 16 bit and 32 bit pointer registers. */
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&& (!Nmode || ((mode & SIZE) != L_32)))
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as_bad (_("Wrong size pointer register for architecture."));
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op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC;
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op->reg = num;
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@ -836,7 +840,9 @@ get_operand (ptr, op, direction)
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*ptr = src;
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return;
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}
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if ((mode & SIZE) != PSIZE)
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if (((mode & SIZE) != PSIZE)
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/* For Normal mode accept 16 bit and 32 bit pointer registers. */
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&& (!Nmode || ((mode & SIZE) != L_32)))
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as_bad (_("Wrong size pointer register for architecture."));
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op->mode = direction | IND | PSIZE;
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@ -1855,6 +1861,7 @@ fix_operand_size (operand, size)
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is safe. get_specific() will relax L_24 into L_32 where
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necessary. */
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if (Hmode
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&& !Nmode
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&& (operand->exp.X_add_number < -32768
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|| operand->exp.X_add_number > 32767
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|| operand->exp.X_add_symbol != 0
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