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merge from d30v-970225-branch
This commit is contained in:
Ken Raeburn
parent
2199f848c0
commit
d51bcb7064
opcodes
@ -1,3 +1,55 @@
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start-sanitize-d30v
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Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com>
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Merge changes from Martin Hunt:
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* d30v-opc.c: Change mvfacc to accept 6-bit unsigned values.
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* d30v-opc.c (pre_defined_registers): Add control registers from 0-63.
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(d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix
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rot2h, sra2h, and srl2h to use new SHORT_A5S format.
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* d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes.
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* d30v-dis.c (print_insn): First operand of d*i (delayed
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branch) instructions is relative.
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* d30v-opc.c (d30v_opcode_table): Change form for repeati.
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(d30v_operand_table): Add IMM6S3 type.
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(d30v_format_table): Change SHORT_D2. Add LONG_Db.
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* d30v-dis.c: Fix bug with ".s" and ".l" extensions
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and cmp instructions.
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* d30v-opc.c: Correct entries for repeat*, and sat*.
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Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
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types. Correct several formats.
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* d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
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* d30v-opc.c (pre_defined_registers): Change control registers.
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* d30v-opc.c (d30v_format_table): Correct SHORT_C1 and
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SHORT_C2. Manual was incorrect.
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* d30v-dis.c (lookup_opcode): Return value now indicates
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if an opcode has a short and a long form. Used for deciding
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to append a ".s" or ".l".
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(print_insn): Append a ".s" to an instruction if it is
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the short form and ".l" if it is a long form. Do not append
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anything if the instruction has only one possible size.
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* d30v-opc.c: Change mulx2h to require an even register.
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New form: SHORT_A2; a SHORT_A form that needs an even
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register as the first operand.
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* d30v-dis.c (print_insn_d30v): Fix problem where the last
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instruction was not being disassembled if there were an odd
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number of instructions.
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* d30v-opc.c (SHORT_M2, LONG_M2): Two new forms.
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end-sanitize-d30v
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start-sanitize-v850e
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Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com>
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@ -33,25 +33,75 @@ const struct pd_reg pre_defined_registers[] =
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{
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{ "a0", NULL, OPERAND_ACC+0 },
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{ "a1", NULL, OPERAND_ACC+1 },
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{ "bpc", NULL, OPERAND_CONTROL+2 },
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{ "bpsw", NULL, OPERAND_CONTROL+3 },
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{ "bpc", NULL, OPERAND_CONTROL+3 },
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{ "bpsw", NULL, OPERAND_CONTROL+1 },
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{ "c", "c", OPERAND_FLAG+7 },
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{ "cr0", "pc", OPERAND_CONTROL },
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{ "cr1", "psw", OPERAND_CONTROL+1 },
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{ "cr10", "mod_e", OPERAND_CONTROL+10 },
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{ "cr11", "iba", OPERAND_CONTROL+11 },
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{ "cr0", "psw", OPERAND_CONTROL },
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{ "cr1", "bpsw", OPERAND_CONTROL+1 },
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{ "cr10", "mod_s", OPERAND_CONTROL+10 },
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{ "cr11", "mod_e", OPERAND_CONTROL+11 },
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{ "cr12", NULL, OPERAND_CONTROL+12 },
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{ "cr13", NULL, OPERAND_CONTROL+13 },
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{ "cr14", NULL, OPERAND_CONTROL+14 },
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{ "cr14", "iba", OPERAND_CONTROL+14 },
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{ "cr15", NULL, OPERAND_CONTROL+15 },
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{ "cr2", "bpc", OPERAND_CONTROL+2 },
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{ "cr3", "bpsw", OPERAND_CONTROL+3 },
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{ "cr4", NULL, OPERAND_CONTROL+4 },
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{ "cr5", NULL, OPERAND_CONTROL+5 },
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{ "cr6", "rpt_c", OPERAND_CONTROL+6 },
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{ "cr7", "rpt_s", OPERAND_CONTROL+7 },
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{ "cr8", "rpt_e", OPERAND_CONTROL+8 },
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{ "cr9", "mod_s", OPERAND_CONTROL+9 },
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{ "cr16", NULL, OPERAND_CONTROL+16 },
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{ "cr17", NULL, OPERAND_CONTROL+17 },
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{ "cr18", NULL, OPERAND_CONTROL+18 },
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{ "cr19", NULL, OPERAND_CONTROL+19 },
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{ "cr2", "pc", OPERAND_CONTROL+2 },
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{ "cr20", NULL, OPERAND_CONTROL+20 },
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{ "cr21", NULL, OPERAND_CONTROL+21 },
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{ "cr22", NULL, OPERAND_CONTROL+22 },
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{ "cr23", NULL, OPERAND_CONTROL+23 },
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{ "cr24", NULL, OPERAND_CONTROL+24 },
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{ "cr25", NULL, OPERAND_CONTROL+25 },
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{ "cr26", NULL, OPERAND_CONTROL+26 },
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{ "cr27", NULL, OPERAND_CONTROL+27 },
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{ "cr28", NULL, OPERAND_CONTROL+28 },
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{ "cr29", NULL, OPERAND_CONTROL+29 },
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{ "cr3", "bpc", OPERAND_CONTROL+3 },
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{ "cr30", NULL, OPERAND_CONTROL+30 },
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{ "cr31", NULL, OPERAND_CONTROL+31 },
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{ "cr32", NULL, OPERAND_CONTROL+32 },
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{ "cr33", NULL, OPERAND_CONTROL+33 },
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{ "cr34", NULL, OPERAND_CONTROL+34 },
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{ "cr35", NULL, OPERAND_CONTROL+35 },
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{ "cr36", NULL, OPERAND_CONTROL+36 },
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{ "cr37", NULL, OPERAND_CONTROL+37 },
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{ "cr38", NULL, OPERAND_CONTROL+38 },
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{ "cr39", NULL, OPERAND_CONTROL+39 },
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{ "cr4", "dpsw", OPERAND_CONTROL+4 },
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{ "cr40", NULL, OPERAND_CONTROL+40 },
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{ "cr41", NULL, OPERAND_CONTROL+41 },
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{ "cr42", NULL, OPERAND_CONTROL+42 },
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{ "cr43", NULL, OPERAND_CONTROL+43 },
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{ "cr44", NULL, OPERAND_CONTROL+44 },
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{ "cr45", NULL, OPERAND_CONTROL+45 },
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{ "cr46", NULL, OPERAND_CONTROL+46 },
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{ "cr47", NULL, OPERAND_CONTROL+47 },
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{ "cr48", NULL, OPERAND_CONTROL+48 },
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{ "cr49", NULL, OPERAND_CONTROL+49 },
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{ "cr5","dpc", OPERAND_CONTROL+5 },
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{ "cr50", NULL, OPERAND_CONTROL+50 },
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{ "cr51", NULL, OPERAND_CONTROL+51 },
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{ "cr52", NULL, OPERAND_CONTROL+52 },
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{ "cr53", NULL, OPERAND_CONTROL+53 },
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{ "cr54", NULL, OPERAND_CONTROL+54 },
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{ "cr55", NULL, OPERAND_CONTROL+55 },
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{ "cr56", NULL, OPERAND_CONTROL+56 },
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{ "cr57", NULL, OPERAND_CONTROL+57 },
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{ "cr58", NULL, OPERAND_CONTROL+58 },
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{ "cr59", NULL, OPERAND_CONTROL+59 },
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{ "cr6", NULL, OPERAND_CONTROL+6 },
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{ "cr60", NULL, OPERAND_CONTROL+60 },
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{ "cr61", NULL, OPERAND_CONTROL+61 },
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{ "cr62", NULL, OPERAND_CONTROL+62 },
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{ "cr63", NULL, OPERAND_CONTROL+63 },
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{ "cr7", "rpt_c", OPERAND_CONTROL+7 },
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{ "cr8", "rpt_s", OPERAND_CONTROL+8 },
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{ "cr9", "rpt_e", OPERAND_CONTROL+9 },
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{ "dpc", NULL, OPERAND_CONTROL+5 },
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{ "dpsw", NULL, OPERAND_CONTROL+4 },
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{ "f0", NULL, OPERAND_FLAG+0 },
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{ "f1", NULL, OPERAND_FLAG+1 },
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{ "f2", NULL, OPERAND_FLAG+2 },
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@ -60,12 +110,12 @@ const struct pd_reg pre_defined_registers[] =
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{ "f5", "v", OPERAND_FLAG+5 },
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{ "f6", "va", OPERAND_FLAG+6 },
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{ "f7", "c", OPERAND_FLAG+7 },
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{ "iba", NULL, OPERAND_CONTROL+11 },
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{ "iba", NULL, OPERAND_CONTROL+14 },
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{ "link", "r62", 62 },
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{ "mod_e", NULL, OPERAND_CONTROL+10 },
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{ "mod_s", NULL, OPERAND_CONTROL+9 },
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{ "pc", NULL, OPERAND_CONTROL+0 },
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{ "psw", NULL, OPERAND_CONTROL+1 },
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{ "mod_e", NULL, OPERAND_CONTROL+11 },
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{ "mod_s", NULL, OPERAND_CONTROL+10 },
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{ "pc", NULL, OPERAND_CONTROL+2 },
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{ "psw", NULL, OPERAND_CONTROL },
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{ "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 },
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{ "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 },
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{ "r0", "0", 0 },
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@ -132,9 +182,9 @@ const struct pd_reg pre_defined_registers[] =
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{ "r7", NULL, 7 },
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{ "r8", NULL, 8 },
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{ "r9", NULL, 9 },
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{ "rpt_c", NULL, OPERAND_CONTROL+6 },
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{ "rpt_e", NULL, OPERAND_CONTROL+8 },
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{ "rpt_s", NULL, OPERAND_CONTROL+7 },
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{ "rpt_c", NULL, OPERAND_CONTROL+7 },
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{ "rpt_e", NULL, OPERAND_CONTROL+9 },
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{ "rpt_s", NULL, OPERAND_CONTROL+8 },
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{ "s", NULL, OPERAND_FLAG+4 },
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{ "sp", NULL, 63 },
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{ "v", NULL, OPERAND_FLAG+5 },
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@ -165,7 +215,7 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
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{ "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 },
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{ "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
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{ "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
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{ "bclr", LOGIC, 0x3, { SHORT_A }, EITHER, 0, 0, 0 },
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@ -177,13 +227,14 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL },
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{ "btst", LOGIC, 0, { SHORT_AF }, EITHER, 0, FLAG_X, 0 },
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{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 },
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{ "cmpu", LOGIC, 0xD, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 },
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{ "btst", LOGIC, 0, { SHORT_AF }, EITHER, 0, 0, 0 },
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{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
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{ "cmpu", LOGIC, 0xD, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
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{ "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL },
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{ "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL },
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{ "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL },
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{ "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL },
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{ "dbt", BRA, 0xb, { SHORT_NONE }, MU, 0, 0, 0 },
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{ "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS },
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{ "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS },
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{ "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS },
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@ -198,10 +249,10 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
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{ "ld2h", IMEM, 0x3, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld2w", IMEM, 0x6, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld4bh", IMEM, 0x5, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld4bhu", IMEM, 0xd, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
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{ "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
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{ "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
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{ "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
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{ "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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{ "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
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@ -225,7 +276,7 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulx", IALU2, 0x18, { SHORT_AA }, IU, 0, 0, 0 },
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{ "mulx2h", IALU2, 0x1, { SHORT_A }, IU, 0, 0, 0 },
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{ "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, 0, 0, 0 },
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{ "mulxs", IALU2, 0x19, { SHORT_AA }, IU, 0, 0, 0 },
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{ "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
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{ "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
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@ -233,28 +284,33 @@ const struct d30v_opcode d30v_opcode_table[] = {
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{ "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
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{ "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
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{ "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
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{ "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, FLAG_X, FLAG_X, 0 },
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{ "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
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{ "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
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{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 },
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{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
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{ "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM, 0 },
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{ "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, 0 },
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{ "repeati", BRA, 0x1a, { SHORT_D2, LONG_D }, MU, FLAG_RP, FLAG_RP, 0 },
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{ "repeati", BRA, 0x1a, { SHORT_D2B, LONG_Db }, MU, FLAG_RP, FLAG_RP, 0 },
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{ "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "sat", IALU2, 0x8, { SHORT_A }, IU, 0, 0, 0 },
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{ "sat2h", IALU2, 0x9, { SHORT_A }, IU, 0, 0, 0 },
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{ "sathl", IALU2, 0x1c, { SHORT_A }, IU, 0, 0, 0 },
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{ "sathh", IALU2, 0x1d, { SHORT_A }, IU, 0, 0, 0 },
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{ "satz", IALU2, 0xa, { SHORT_A }, IU, 0, 0, 0 },
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{ "satz2h", IALU2, 0xb, { SHORT_A }, IU, 0, 0, 0 },
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{ "rot2h", LOGIC, 0x15, { SHORT_A5S }, EITHER, 0, 0, 0 },
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{ "rtd", BRA, 0xa, { SHORT_NONE }, MU, 0, 0, 0 },
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{ "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
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{ "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
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{ "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, 0, 0, 0 },
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{ "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, 0, 0, 0 },
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{ "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
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{ "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
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{ "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "sra2h", LOGIC, 0x11, { SHORT_A5S }, EITHER, 0, 0, 0 },
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{ "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "src", LOGIC, 0x16, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "srl2h", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "st2h", IMEM, 0x13, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "st2w", IMEM, 0x16, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "st4hb", IMEM, 0x15, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
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{ "srl2h", LOGIC, 0x13, { SHORT_A5S }, EITHER, 0, 0, 0 },
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{ "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
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{ "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
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{ "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
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{ "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
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{ "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
|
||||
{ "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
|
||||
{ "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
|
||||
@ -272,7 +328,7 @@ const struct d30v_opcode d30v_opcode_table[] = {
|
||||
{ "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
|
||||
{ "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM, 0 },
|
||||
{ "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
|
||||
{ "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 },
|
||||
{ "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },
|
||||
{ NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
@ -285,7 +341,9 @@ const struct d30v_operand d30v_operand_table[] =
|
||||
{ 0, 0, 0, 0 },
|
||||
#define Ra (UNUSED + 1)
|
||||
{ 6, 6, 0, OPERAND_REG|OPERAND_DEST },
|
||||
#define Rb (Ra + 1)
|
||||
#define Ra2 (Ra + 1)
|
||||
{ 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG },
|
||||
#define Rb (Ra2 + 1)
|
||||
{ 6, 6, 6, OPERAND_REG },
|
||||
#define Rc (Rb + 1)
|
||||
{ 6, 6, 12, OPERAND_REG },
|
||||
@ -294,16 +352,24 @@ const struct d30v_operand d30v_operand_table[] =
|
||||
#define Ab (Aa + 1)
|
||||
{ 6, 1, 6, OPERAND_ACC|OPERAND_REG },
|
||||
#define IMM5 (Ab + 1)
|
||||
{ 6, 5, 12, OPERAND_NUM },
|
||||
#define IMM5U (IMM5 + 1)
|
||||
{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
|
||||
#define IMM5S3 (IMM5 + 1)
|
||||
#define IMM5S3 (IMM5U + 1)
|
||||
{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
|
||||
#define IMM6 (IMM5S3 + 1)
|
||||
{ 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
|
||||
#define IMM12 (IMM6 + 1)
|
||||
{ 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED },
|
||||
#define IMM12S3 (IMM12 + 1)
|
||||
{ 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
|
||||
#define IMM18S3 (IMM12S3 + 1)
|
||||
#define IMM6U (IMM6 + 1)
|
||||
{ 6, 6, 0, OPERAND_NUM },
|
||||
#define IMM6U2 (IMM6U + 1)
|
||||
{ 6, 6, 12, OPERAND_NUM },
|
||||
#define IMM6S3 (IMM6U2 + 1)
|
||||
{ 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT },
|
||||
#define IMM12S3 (IMM6S3 + 1)
|
||||
{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
|
||||
#define IMM12S3U (IMM12S3 + 1)
|
||||
{ 12, 12, 12, OPERAND_NUM|OPERAND_SHIFT },
|
||||
#define IMM18S3 (IMM12S3U + 1)
|
||||
{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
|
||||
#define IMM32 (IMM18S3 + 1)
|
||||
{ 32, 32, 0, OPERAND_NUM },
|
||||
@ -324,9 +390,9 @@ const struct d30v_operand d30v_operand_table[] =
|
||||
#define ATMINUS (MINUS + 1) /* predecrement */
|
||||
{ 0, 0, 0, OPERAND_ATMINUS},
|
||||
#define Ca (ATMINUS + 1) /* control register */
|
||||
{ 6, 4, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
|
||||
{ 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
|
||||
#define Cb (Ca + 1) /* control register */
|
||||
{ 6, 4, 6, OPERAND_REG|OPERAND_CONTROL},
|
||||
{ 6, 6, 6, OPERAND_REG|OPERAND_CONTROL},
|
||||
#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */
|
||||
{ 3, 3, -3, OPERAND_NAME},
|
||||
#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */
|
||||
@ -343,25 +409,32 @@ const struct d30v_format d30v_format_table[] =
|
||||
{ SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
|
||||
{ SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
|
||||
{ SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
|
||||
{ SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
|
||||
{ SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
|
||||
{ SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
|
||||
{ SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
|
||||
{ SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
|
||||
{ SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
|
||||
{ SHORT_B1, 0, { Rc } }, /* Rc */
|
||||
{ SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
|
||||
{ SHORT_B3, 0, { Ra, Rc } }, /* Ra,Rc */
|
||||
{ SHORT_B3, 2, { Ra, IMM12 } }, /* Ra,imm12 */
|
||||
{ SHORT_B3, 2, { Ra, IMM12S3 } }, /* Ra,imm12 */
|
||||
{ SHORT_B3b, 1, { Ra, Rc } }, /* Ra,Rc */
|
||||
{ SHORT_B3b, 3, { Ra, IMM12 } }, /* Ra,imm12 */
|
||||
{ SHORT_B3b, 3, { Ra, IMM12S3 } }, /* Ra,imm12 */
|
||||
{ SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */
|
||||
{ SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */
|
||||
{ SHORT_D2, 0, { IMM6, Rc } }, /* imm6,Rc */
|
||||
{ SHORT_D2, 2, { IMM6, IMM12S3 } }, /* imm6,imm12s3 */
|
||||
{ SHORT_D2, 0, { IMM6S3, Rc } }, /* imm6s3,Rc */
|
||||
{ SHORT_D2, 2, { IMM6S3, IMM12S3 } }, /* imm6s3,imm12s3 */
|
||||
{ SHORT_D2B, 0, { IMM6U, Rc } }, /* imm6u,Rc */
|
||||
{ SHORT_D2B, 2, { IMM6U, IMM12S3U } }, /* imm6u,imm12s3u */
|
||||
{ SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
|
||||
{ SHORT_U, 2, { Ra, IMM12 } }, /* Ra,imm12 (repeat) */
|
||||
{ SHORT_U, 2, { Ra, IMM12S3 } }, /* Ra,imm12 (repeat) */
|
||||
{ SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
|
||||
{ SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
|
||||
{ SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
|
||||
{ SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */
|
||||
{ SHORT_T, 2, { IMM5S3 } }, /* imm5s3 (trap) */
|
||||
{ SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
|
||||
{ SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
|
||||
{ SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
|
||||
{ SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
|
||||
{ SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */
|
||||
@ -370,21 +443,27 @@ const struct d30v_format d30v_format_table[] =
|
||||
{ SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
|
||||
{ SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */
|
||||
{ SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */
|
||||
{ SHORT_RA, 2, { Ra, Ab, IMM5 } }, /* Ra,Ab,imm5 */
|
||||
{ SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */
|
||||
{ SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */
|
||||
{ SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */
|
||||
{ SHORT_C1, 2, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
|
||||
{ SHORT_C2, 2, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
|
||||
{ SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
|
||||
{ SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
|
||||
{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
|
||||
{ SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
|
||||
{ SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
|
||||
{ SHORT_A5S, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
|
||||
{ SHORT_A5S, 2, { Ra, Rb, IMM5U } }, /* Ra,Rb,imm5u (shifts) */
|
||||
{ SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
|
||||
{ LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
|
||||
{ LONG_U, 2, { IMM32 } }, /* imm32 */
|
||||
{ LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */
|
||||
{ LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
|
||||
{ LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
|
||||
{ LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
|
||||
{ LONG_2, 2, { Ra, IMM32 } }, /* Ra,imm32 */
|
||||
{ LONG_2b, 3, { Ra, IMM32 } }, /* Ra,imm32 */
|
||||
{ LONG_D, 2, { IMM6, IMM32 } }, /* imm6,imm32 */
|
||||
{ LONG_D, 2, { IMM6S3, IMM32 } }, /* imm6s3,imm32 */
|
||||
{ LONG_Db, 2, { IMM6U, IMM32 } }, /* imm6,imm32 */
|
||||
{ 0, 0, { 0 } },
|
||||
};
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user