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2007-10-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (v_mode): Defined as previous one + 1. (w_mode): Likewise. (d_mode): Likewise. (q_mode): Likewise. (t_mode): Likewise. (x_mode): Likewise. (m_mode): Likewise. (cond_jump_mode): Likewise. (loop_jcxz_mode): Likewise. (dq_mode): Likewise. (dqw_mode): Likewise. (f_mode): Likewise. (const_1_mode): Likewise. (stack_v_mode): Likewise. (z_mode): Likewise. (o_mode): Likewise. (dqb_mode): Likewise. (dqd_mode): Likewise. (es_reg): Likewise. (cs_reg): Likewise. (ss_reg): Likewise. (ds_reg): Likewise. (fs_reg): Likewise. (gs_reg): Likewise. (eAX_reg): Likewise. (eCX_reg): Likewise. (eDX_reg): Likewise. (eBX_reg): Likewise. (eSP_reg): Likewise. (eBP_reg): Likewise. (eSI_reg): Likewise. (eDI_reg): Likewise. (al_reg): Likewise. (cl_reg): Likewise. (dl_reg): Likewise. (bl_reg): Likewise. (ah_reg): Likewise. (ch_reg): Likewise. (dh_reg): Likewise. (bh_reg): Likewise. (ax_reg): Likewise. (cx_reg): Likewise. (dx_reg): Likewise. (bx_reg): Likewise. (sp_reg): Likewise. (bp_reg): Likewise. (si_reg): Likewise. (di_reg): Likewise. (rAX_reg): Likewise. (rCX_reg): Likewise. (rDX_reg): Likewise. (rBX_reg): Likewise. (rSP_reg): Likewise. (rBP_reg): Likewise. (rSI_reg): Likewise. (rDI_reg): Likewise. (z_mode_ax_reg): Likewise. (indir_dx_reg): Likewise. (DREX_OC1): Updated. (DREX_NO_OC0): Likewise. (DREX_MASK): Likewise. (MAX_BYTEMODE): New. Issue an error if MAX_BYTEMODE is not less than DREX_OC1.
This commit is contained in:
H.J. Lu
parent
4be4395321
commit
d55ee72f29
@ -1,3 +1,69 @@
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2007-10-10 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (v_mode): Defined as previous one + 1.
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(w_mode): Likewise.
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(d_mode): Likewise.
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(q_mode): Likewise.
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(t_mode): Likewise.
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(x_mode): Likewise.
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(m_mode): Likewise.
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(cond_jump_mode): Likewise.
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(loop_jcxz_mode): Likewise.
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(dq_mode): Likewise.
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(dqw_mode): Likewise.
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(f_mode): Likewise.
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(const_1_mode): Likewise.
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(stack_v_mode): Likewise.
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(z_mode): Likewise.
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(o_mode): Likewise.
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(dqb_mode): Likewise.
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(dqd_mode): Likewise.
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(es_reg): Likewise.
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(cs_reg): Likewise.
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(ss_reg): Likewise.
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(ds_reg): Likewise.
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(fs_reg): Likewise.
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(gs_reg): Likewise.
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(eAX_reg): Likewise.
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(eCX_reg): Likewise.
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(eDX_reg): Likewise.
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(eBX_reg): Likewise.
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(eSP_reg): Likewise.
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(eBP_reg): Likewise.
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(eSI_reg): Likewise.
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(eDI_reg): Likewise.
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(al_reg): Likewise.
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(cl_reg): Likewise.
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(dl_reg): Likewise.
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(bl_reg): Likewise.
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(ah_reg): Likewise.
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(ch_reg): Likewise.
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(dh_reg): Likewise.
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(bh_reg): Likewise.
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(ax_reg): Likewise.
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(cx_reg): Likewise.
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(dx_reg): Likewise.
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(bx_reg): Likewise.
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(sp_reg): Likewise.
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(bp_reg): Likewise.
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(si_reg): Likewise.
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(di_reg): Likewise.
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(rAX_reg): Likewise.
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(rCX_reg): Likewise.
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(rDX_reg): Likewise.
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(rBX_reg): Likewise.
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(rSP_reg): Likewise.
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(rBP_reg): Likewise.
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(rSI_reg): Likewise.
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(rDI_reg): Likewise.
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(z_mode_ax_reg): Likewise.
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(indir_dx_reg): Likewise.
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(DREX_OC1): Updated.
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(DREX_NO_OC0): Likewise.
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(DREX_MASK): Likewise.
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(MAX_BYTEMODE): New. Issue an error if MAX_BYTEMODE is not
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less than DREX_OC1.
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2007-10-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c: Updated comments for 'Y'.
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@ -361,76 +361,99 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define AFLAG 2
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#define DFLAG 1
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#define b_mode 1 /* byte operand */
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#define v_mode 2 /* operand size depends on prefixes */
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#define w_mode 3 /* word operand */
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#define d_mode 4 /* double word operand */
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#define q_mode 5 /* quad word operand */
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#define t_mode 6 /* ten-byte operand */
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#define x_mode 7 /* 16-byte XMM operand */
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#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
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#define cond_jump_mode 9
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#define loop_jcxz_mode 10
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#define dq_mode 11 /* operand size depends on REX prefixes. */
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#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
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#define f_mode 13 /* 4- or 6-byte pointer operand */
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#define const_1_mode 14
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#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
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#define z_mode 16 /* non-quad operand size depends on prefixes */
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#define o_mode 17 /* 16-byte operand */
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#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
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#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
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/* byte operand */
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#define b_mode 1
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/* operand size depends on prefixes */
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#define v_mode (b_mode + 1)
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/* word operand */
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#define w_mode (v_mode + 1)
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/* double word operand */
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#define d_mode (w_mode + 1)
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/* quad word operand */
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#define q_mode (d_mode + 1)
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/* ten-byte operand */
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#define t_mode (q_mode + 1)
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/* 16-byte XMM operand */
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#define x_mode (t_mode + 1)
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/* d_mode in 32bit, q_mode in 64bit mode. */
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#define m_mode (x_mode + 1)
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#define cond_jump_mode (m_mode + 1)
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#define loop_jcxz_mode (cond_jump_mode + 1)
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/* operand size depends on REX prefixes. */
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#define dq_mode (loop_jcxz_mode + 1)
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/* registers like dq_mode, memory like w_mode. */
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#define dqw_mode (dq_mode + 1)
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/* 4- or 6-byte pointer operand */
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#define f_mode (dqw_mode + 1)
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#define const_1_mode (f_mode + 1)
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/* v_mode for stack-related opcodes. */
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#define stack_v_mode (const_1_mode + 1)
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/* non-quad operand size depends on prefixes */
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#define z_mode (stack_v_mode + 1)
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/* 16-byte operand */
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#define o_mode (z_mode + 1)
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/* registers like dq_mode, memory like b_mode. */
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#define dqb_mode (o_mode + 1)
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/* registers like dq_mode, memory like d_mode. */
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#define dqd_mode (dqb_mode + 1)
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/* Flags that are OR'ed into the bytemode field to pass extra information. */
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#define DREX_OC1 0x4000 /* OC1 bit set */
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#define DREX_NO_OC0 0x2000 /* OC0 bit not used */
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#define DREX_MASK 0x6000 /* mask to delete */
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#define es_reg (dqd_mode + 1)
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#define cs_reg (es_reg + 1)
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#define ss_reg (cs_reg + 1)
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#define ds_reg (ss_reg + 1)
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#define fs_reg (ds_reg + 1)
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#define gs_reg (fs_reg + 1)
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#define es_reg 100
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#define cs_reg 101
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#define ss_reg 102
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#define ds_reg 103
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#define fs_reg 104
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#define gs_reg 105
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#define eAX_reg (gs_reg + 1)
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#define eCX_reg (eAX_reg + 1)
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#define eDX_reg (eCX_reg + 1)
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#define eBX_reg (eDX_reg + 1)
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#define eSP_reg (eBX_reg + 1)
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#define eBP_reg (eSP_reg + 1)
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#define eSI_reg (eBP_reg + 1)
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#define eDI_reg (eSI_reg + 1)
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#define eAX_reg 108
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#define eCX_reg 109
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#define eDX_reg 110
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#define eBX_reg 111
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#define eSP_reg 112
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#define eBP_reg 113
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#define eSI_reg 114
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#define eDI_reg 115
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#define al_reg (eDI_reg + 1)
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#define cl_reg (al_reg + 1)
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#define dl_reg (cl_reg + 1)
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#define bl_reg (dl_reg + 1)
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#define ah_reg (bl_reg + 1)
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#define ch_reg (ah_reg + 1)
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#define dh_reg (ch_reg + 1)
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#define bh_reg (dh_reg + 1)
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#define al_reg 116
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#define cl_reg 117
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#define dl_reg 118
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#define bl_reg 119
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#define ah_reg 120
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#define ch_reg 121
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#define dh_reg 122
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#define bh_reg 123
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#define ax_reg (bh_reg + 1)
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#define cx_reg (ax_reg + 1)
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#define dx_reg (cx_reg + 1)
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#define bx_reg (dx_reg + 1)
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#define sp_reg (bx_reg + 1)
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#define bp_reg (sp_reg + 1)
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#define si_reg (bp_reg + 1)
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#define di_reg (si_reg + 1)
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#define ax_reg 124
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#define cx_reg 125
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#define dx_reg 126
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#define bx_reg 127
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#define sp_reg 128
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#define bp_reg 129
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#define si_reg 130
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#define di_reg 131
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#define rAX_reg (di_reg + 1)
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#define rCX_reg (rAX_reg + 1)
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#define rDX_reg (rCX_reg + 1)
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#define rBX_reg (rDX_reg + 1)
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#define rSP_reg (rBX_reg + 1)
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#define rBP_reg (rSP_reg + 1)
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#define rSI_reg (rBP_reg + 1)
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#define rDI_reg (rSI_reg + 1)
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#define rAX_reg 132
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#define rCX_reg 133
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#define rDX_reg 134
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#define rBX_reg 135
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#define rSP_reg 136
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#define rBP_reg 137
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#define rSI_reg 138
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#define rDI_reg 139
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#define z_mode_ax_reg (rDI_reg + 1)
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#define indir_dx_reg (z_mode_ax_reg + 1)
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#define z_mode_ax_reg 149
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#define indir_dx_reg 150
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#define MAX_BYTEMODE indir_dx_reg
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/* Flags that are OR'ed into the bytemode field to pass extra
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information. */
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#define DREX_OC1 0x10000 /* OC1 bit set */
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#define DREX_NO_OC0 0x20000 /* OC0 bit not used */
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#define DREX_MASK 0x40000 /* mask to delete */
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#if MAX_BYTEMODE >= DREX_OC1
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#error MAX_BYTEMODE must be less than DREX_OC1
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#endif
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#define FLOATCODE 1
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#define USE_REG_TABLE 2
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