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2004-04-29 Andrew Cagney <cagney@redhat.com>
* mips-tdep.c (mips_register_type): Re-write, handle 32-bit ABI registers correctly. (print_gp_register_row, mips32_heuristic_proc_desc) (mips_n32n64_push_dummy_call, mips_o32_push_dummy_call) (mips_o64_push_dummy_call, mips_eabi_push_dummy_call): Eliminate references to mips_isa_regsize.
This commit is contained in:
Andrew Cagney
parent
9aae080b54
commit
d5ac5a39d8
@ -1,3 +1,12 @@
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2004-04-29 Andrew Cagney <cagney@redhat.com>
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* mips-tdep.c (mips_register_type): Re-write, handle 32-bit ABI
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registers correctly.
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(print_gp_register_row, mips32_heuristic_proc_desc)
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(mips_n32n64_push_dummy_call, mips_o32_push_dummy_call)
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(mips_o64_push_dummy_call, mips_eabi_push_dummy_call): Eliminate
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references to mips_isa_regsize.
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2004-04-29 Andrew Cagney <cagney@redhat.com>
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* mips-tdep.c (struct gdbarch_tdep): Delete
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@ -717,24 +717,38 @@ mips_register_type (struct gdbarch *gdbarch, int regnum)
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internal_error (__FILE__, __LINE__, "bad switch");
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}
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}
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else if (regnum >=
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(NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status)
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&& regnum <= NUM_REGS + LAST_EMBED_REGNUM)
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/* The pseudo/cooked view of the embedded registers is always
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32-bit. The raw view is handled below. */
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return builtin_type_int32;
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else if (regnum >= NUM_REGS && mips_isa_regsize (gdbarch)
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&& gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
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/* The target, while using a 64-bit register buffer, is only
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transfering 32-bits of each integer register. Reflect this in
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the cooked/pseudo register value. */
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return builtin_type_int32;
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else if (mips_isa_regsize (gdbarch) == 8)
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/* 64-bit ISA. */
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return builtin_type_int64;
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else if (regnum < NUM_REGS)
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{
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/* The raw or ISA registers. These are all sized according to
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the ISA regsize. */
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if (mips_isa_regsize (gdbarch) == 4)
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return builtin_type_int32;
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else
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return builtin_type_int64;
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}
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else
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/* 32-bit ISA. */
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return builtin_type_int32;
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{
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/* The cooked or ABI registers. These are sized according to
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the ABI (with a few complications). */
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if (regnum >= (NUM_REGS
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+ mips_regnum (current_gdbarch)->fp_control_status)
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&& regnum <= NUM_REGS + LAST_EMBED_REGNUM)
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/* The pseudo/cooked view of the embedded registers is always
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32-bit. The raw view is handled below. */
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return builtin_type_int32;
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else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
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/* The target, while possibly using a 64-bit register buffer,
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is only transfering 32-bits of each integer register.
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Reflect this in the cooked/pseudo (ABI) register value. */
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return builtin_type_int32;
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else if (mips_abi_regsize (gdbarch) == 4)
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/* The ABI is restricted to 32-bit registers (the ISA could be
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32- or 64-bit). */
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return builtin_type_int32;
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else
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/* 64-bit ABI. */
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return builtin_type_int64;
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}
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}
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/* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
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@ -2170,12 +2184,10 @@ restart:
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}
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else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
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{
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/* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
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but the register size used is only 32 bits. Make the address
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for the saved register point to the lower 32 bits. */
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/* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
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$ra. */
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PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
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set_reg_offset (temp_saved_regs, reg,
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sp + low_word + 8 - mips_isa_regsize (current_gdbarch));
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set_reg_offset (temp_saved_regs, reg, sp + low_word);
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}
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else if (high_word == 0x27be) /* addiu $30,$sp,size */
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{
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@ -2910,10 +2922,10 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
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register-sized pieces. Large arguments are split between
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registers and stack. */
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/* Note: structs whose size is not a multiple of
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mips_isa_regsize() are treated specially: Irix cc passes them
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in registers where gcc sometimes puts them on the stack.
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For maximum compatibility, we will put them in both
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places. */
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mips_abi_regsize() are treated specially: Irix cc passes
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them in registers where gcc sometimes puts them on the
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stack. For maximum compatibility, we will put them in
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both places. */
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int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
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&& (len % mips_abi_regsize (gdbarch) != 0));
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@ -3171,10 +3183,10 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
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register-sized pieces. Large arguments are split between
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registers and stack. */
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/* Note: structs whose size is not a multiple of
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mips_isa_regsize() are treated specially: Irix cc passes them
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in registers where gcc sometimes puts them on the stack.
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For maximum compatibility, we will put them in both
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places. */
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mips_abi_regsize() are treated specially: Irix cc passes
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them in registers where gcc sometimes puts them on the
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stack. For maximum compatibility, we will put them in
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both places. */
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int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
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&& (len % mips_abi_regsize (gdbarch) != 0));
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/* Note: Floating-point values that didn't fit into an FP
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@ -3568,10 +3580,10 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
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register-sized pieces. Large arguments are split between
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registers and stack. */
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/* Note: structs whose size is not a multiple of
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mips_isa_regsize() are treated specially: Irix cc passes them
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in registers where gcc sometimes puts them on the stack.
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For maximum compatibility, we will put them in both
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places. */
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mips_abi_regsize() are treated specially: Irix cc passes
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them in registers where gcc sometimes puts them on the
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stack. For maximum compatibility, we will put them in
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both places. */
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int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
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&& (len % mips_abi_regsize (gdbarch) != 0));
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/* Structures should be aligned to eight bytes (even arg registers)
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@ -4021,10 +4033,10 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
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register-sized pieces. Large arguments are split between
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registers and stack. */
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/* Note: structs whose size is not a multiple of
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mips_isa_regsize() are treated specially: Irix cc passes them
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in registers where gcc sometimes puts them on the stack.
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For maximum compatibility, we will put them in both
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places. */
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mips_abi_regsize() are treated specially: Irix cc passes
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them in registers where gcc sometimes puts them on the
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stack. For maximum compatibility, we will put them in
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both places. */
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int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
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&& (len % mips_abi_regsize (gdbarch) != 0));
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/* Structures should be aligned to eight bytes (even arg registers)
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@ -4475,7 +4487,7 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
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struct gdbarch *gdbarch = get_frame_arch (frame);
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/* do values for GP (int) regs */
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char raw_buffer[MAX_REGISTER_SIZE];
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int ncols = (mips_isa_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
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int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
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int col, byte;
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int regnum;
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@ -4490,7 +4502,7 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
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TYPE_CODE_FLT)
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break; /* end the row: reached FP register */
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fprintf_filtered (file,
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mips_isa_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
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mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
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REGISTER_NAME (regnum));
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col++;
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}
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@ -4514,7 +4526,7 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
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error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
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/* pad small registers */
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for (byte = 0;
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byte < (mips_isa_regsize (current_gdbarch)
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byte < (mips_abi_regsize (current_gdbarch)
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- register_size (current_gdbarch, regnum)); byte++)
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printf_filtered (" ");
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/* Now print the register value in hex, endian order. */
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