mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-29 06:50:32 +00:00
* interp.c: OP should be an array of 32bit operands!
(v850_callback): Declare.
(do_format_5): Fix extraction of OP[0].
(sim_size): Remove debugging printf.
(sim_set_callbacks): Do something useful.
(sim_stop_reason): Gross hacks to get c-torture running.
* simops.c: Simplify code for computing targets of bCC
insns. Invert 's' bit if 'ov' bit is set for some
instructions. Fix 'cy' bit handling for numerous
instructions. Make the simulator stop when a halt
instruction is encountered. Very crude support for
emulated syscalls (trap 0).
* v850_sim.h: Include "callback.h" and declare
v850_callback. Items in the operand array are 32bits.
Fixes & syscall stuff.
This commit is contained in:
Jeff Law
parent
7b0af209eb
commit
d81352b8b8
@ -1,3 +1,27 @@
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Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c: OP should be an array of 32bit operands!
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(v850_callback): Declare.
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(do_format_5): Fix extraction of OP[0].
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(sim_size): Remove debugging printf.
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(sim_set_callbacks): Do something useful.
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(sim_stop_reason): Gross hacks to get c-torture running.
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* simops.c: Simplify code for computing targets of bCC
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insns. Invert 's' bit if 'ov' bit is set for some
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instructions. Fix 'cy' bit handling for numerous
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instructions. Make the simulator stop when a halt
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instruction is encountered. Very crude support for
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emulated syscalls (trap 0).
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* v850_sim.h: Include "callback.h" and declare
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v850_callback. Items in the operand array are 32bits.
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Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (sim_resume): Fix code to check for a format 3
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opcode.
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* simops.c: bCC insns only argument is a constant, not a
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register value (duh...)
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Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix "not1" and "set1".
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@ -8,7 +8,10 @@
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#define MEM_SIZE 18 /* V850 memory size is 18 bits XXX */
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uint16 OP[4];
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host_callback *v850_callback;
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uint32 OP[4];
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static struct hash_entry *lookup_hash PARAMS ((uint32 ins));
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@ -161,7 +164,7 @@ do_format_5 (insn)
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struct hash_entry *h;
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h = lookup_hash (insn);
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OP[0] = ((insn & 0x3f) | (((insn >> 17) & 0x7fff) << 6)) << 1;
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OP[0] = (((insn & 0x3f) << 15) | ((insn >> 17) & 0x7fff)) << 1;
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OP[1] = (insn >> 11) & 0x1f;
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(h->ops->func) ();
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}
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@ -233,7 +236,6 @@ sim_size (power)
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fprintf (stderr,"Memory allocation failed.\n");
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exit(1);
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}
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printf ("Allocated %d bytes memory and\n",1<<MEM_SIZE);
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}
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static void
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@ -344,7 +346,7 @@ sim_resume (step, siggnal)
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do_format_4 (inst & 0xffff);
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PC += 2;
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}
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else if ((opcode & 0x3C) == 0x23)
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else if ((opcode & 0x3C) == 0x2C)
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{
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do_format_3 (inst & 0xffff);
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/* No PC update, it's done in the instruction. */
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@ -412,25 +414,23 @@ void
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sim_set_callbacks(p)
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host_callback *p;
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{
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/* callback = p; */
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v850_callback = p;
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}
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/* All the code for exiting, signals, etc needs to be revamped. */
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This is enough to get c-torture limping though. */
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void
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sim_stop_reason (reason, sigrc)
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enum sim_stop *reason;
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int *sigrc;
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{
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*reason = sim_stopped;
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if (State.exception == SIGQUIT)
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{
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*reason = sim_exited;
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*sigrc = State.exception;
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}
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*sigrc = 0;
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else
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{
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*reason = sim_stopped;
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*sigrc = State.exception;
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}
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*sigrc = State.exception;
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}
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void
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@ -191,8 +191,7 @@ OP_580 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_OV) != 0)
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@ -208,8 +207,7 @@ OP_581 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_CY) != 0)
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@ -225,8 +223,7 @@ OP_582 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_Z) != 0)
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@ -242,8 +239,7 @@ OP_583 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
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@ -259,8 +255,7 @@ OP_584 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_S) != 0)
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@ -276,8 +271,7 @@ OP_585 ()
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unsigned int op0;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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State.pc += op0;
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}
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@ -288,8 +282,7 @@ OP_586 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
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@ -305,8 +298,7 @@ OP_587 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_Z) != 0)
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@ -323,8 +315,7 @@ OP_588 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_OV) == 0)
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@ -340,8 +331,7 @@ OP_589 ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_CY) == 0)
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@ -357,8 +347,7 @@ OP_58A ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_Z) == 0)
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@ -374,8 +363,7 @@ OP_58B ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
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@ -391,8 +379,7 @@ OP_58C ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_S) == 0)
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@ -408,8 +395,7 @@ OP_58D ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_SAT) != 0)
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@ -425,8 +411,7 @@ OP_58E ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
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@ -442,8 +427,7 @@ OP_58F ()
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unsigned int op0, psw;
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int temp;
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temp = (State.regs[OP[0]] << 23) >> 23;
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op0 = temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_Z) != 0)
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@ -498,6 +482,10 @@ OP_1C0 ()
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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@ -526,6 +514,10 @@ OP_240 ()
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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@ -554,6 +546,10 @@ OP_600 ()
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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@ -575,10 +571,14 @@ OP_1A0 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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cy = (op1 < op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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@ -600,10 +600,14 @@ OP_180 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op1);
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cy = (op0 < op1);
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ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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@ -694,7 +698,7 @@ OP_1E0 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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cy = (op1 < op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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@ -721,7 +725,7 @@ OP_260 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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cy = (op1 < op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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@ -883,7 +887,7 @@ OP_A0 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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cy = (op1 < op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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@ -919,7 +923,7 @@ OP_660 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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cy = (op1 < op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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@ -951,7 +955,7 @@ OP_80 ()
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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cy = (result < op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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@ -1400,7 +1404,7 @@ OP_16087E0 ()
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void
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OP_12007E0 ()
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{
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abort ();
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State.exception = SIGQUIT;
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}
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/* reti, not supported */
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@ -1414,7 +1418,158 @@ OP_14007E0 ()
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void
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OP_10007E0 ()
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{
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abort ();
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extern int errno;
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/* Trap 0 is used for simulating low-level I/O */
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if (OP[0] == 0)
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{
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#if 0
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char *fstr = State.regs[2] + State.imem;
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printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
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#else
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int save_errno = errno;
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errno = 0;
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/* Registers passed to trap 0 */
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#define FUNC State.regs[6] /* function number, return value */
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#define PARM1 State.regs[7] /* optional parm 1 */
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#define PARM2 State.regs[8] /* optional parm 2 */
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#define PARM3 State.regs[9] /* optional parm 3 */
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/* Registers set by trap 0 */
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#define RETVAL State.regs[10] /* return value */
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#define RETERR State.regs[11] /* return error code */
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/* Turn a pointer in a register into a pointer into real memory. */
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#define MEMPTR(x) ((char *)((x) + State.mem))
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switch (FUNC)
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{
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#if 0
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#if !defined(__GO32__) && !defined(_WIN32)
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case SYS_fork:
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RETVAL = fork ();
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break;
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case SYS_execve:
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RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
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(char **)MEMPTR (PARM3));
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break;
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case SYS_execv:
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RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
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break;
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case SYS_pipe:
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{
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reg_t buf;
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int host_fd[2];
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buf = PARM1;
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RETVAL = pipe (host_fd);
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SW (buf, host_fd[0]);
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buf += sizeof(uint16);
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SW (buf, host_fd[1]);
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}
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break;
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case SYS_wait:
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{
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int status;
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RETVAL = wait (&status);
|
||||
SW (PARM1, status);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
case SYS_read:
|
||||
RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
|
||||
PARM3);
|
||||
break;
|
||||
#endif
|
||||
case SYS_write:
|
||||
if (PARM1 == 1)
|
||||
RETVAL = (int)v850_callback->write_stdout (v850_callback,
|
||||
MEMPTR (PARM2), PARM3);
|
||||
else
|
||||
RETVAL = (int)v850_callback->write (v850_callback, PARM1,
|
||||
MEMPTR (PARM2), PARM3);
|
||||
break;
|
||||
#if 0
|
||||
case SYS_lseek:
|
||||
RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
|
||||
break;
|
||||
case SYS_close:
|
||||
RETVAL = v850_callback->close (v850_callback, PARM1);
|
||||
break;
|
||||
case SYS_open:
|
||||
RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
|
||||
break;
|
||||
#endif
|
||||
case SYS_exit:
|
||||
/* EXIT - caller can look in PARM1 to work out the
|
||||
reason */
|
||||
if (PARM1 == 0xdead || PARM1 == 0x1)
|
||||
State.exception = SIGABRT;
|
||||
else
|
||||
State.exception = SIGQUIT;
|
||||
break;
|
||||
|
||||
#if 0
|
||||
case SYS_stat: /* added at hmsi */
|
||||
/* stat system call */
|
||||
{
|
||||
struct stat host_stat;
|
||||
reg_t buf;
|
||||
|
||||
RETVAL = stat (MEMPTR (PARM1), &host_stat);
|
||||
|
||||
buf = PARM2;
|
||||
|
||||
/* The hard-coded offsets and sizes were determined by using
|
||||
* the D10V compiler on a test program that used struct stat.
|
||||
*/
|
||||
SW (buf, host_stat.st_dev);
|
||||
SW (buf+2, host_stat.st_ino);
|
||||
SW (buf+4, host_stat.st_mode);
|
||||
SW (buf+6, host_stat.st_nlink);
|
||||
SW (buf+8, host_stat.st_uid);
|
||||
SW (buf+10, host_stat.st_gid);
|
||||
SW (buf+12, host_stat.st_rdev);
|
||||
SLW (buf+16, host_stat.st_size);
|
||||
SLW (buf+20, host_stat.st_atime);
|
||||
SLW (buf+28, host_stat.st_mtime);
|
||||
SLW (buf+36, host_stat.st_ctime);
|
||||
}
|
||||
break;
|
||||
|
||||
case SYS_chown:
|
||||
RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
|
||||
break;
|
||||
case SYS_chmod:
|
||||
RETVAL = chmod (MEMPTR (PARM1), PARM2);
|
||||
break;
|
||||
case SYS_utime:
|
||||
/* Cast the second argument to void *, to avoid type mismatch
|
||||
if a prototype is present. */
|
||||
RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
RETERR = errno;
|
||||
errno = save_errno;
|
||||
#endif
|
||||
}
|
||||
else if (OP[0] == 1 )
|
||||
{
|
||||
char *fstr = State.regs[2] + State.mem;
|
||||
puts (fstr);
|
||||
}
|
||||
}
|
||||
|
||||
/* ldsr, reg,reg */
|
||||
|
||||
@ -1,8 +1,11 @@
|
||||
#include <stdio.h>
|
||||
#include <ctype.h>
|
||||
#include "ansidecl.h"
|
||||
#include "callback.h"
|
||||
#include "opcode/v850.h"
|
||||
|
||||
extern host_callback *v850_callback;
|
||||
|
||||
/* FIXME: host defines */
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
@ -29,12 +32,11 @@ struct _state
|
||||
reg_t regs[32]; /* general-purpose registers */
|
||||
reg_t sregs[32]; /* system regsiters, including psw */
|
||||
reg_t pc;
|
||||
uint8 *imem;
|
||||
uint8 *dmem;
|
||||
uint8 *mem;
|
||||
int exception;
|
||||
} State;
|
||||
|
||||
extern uint16 OP[4];
|
||||
extern uint32 OP[4];
|
||||
extern struct simops Simops[];
|
||||
|
||||
#define PC (State.pc)
|
||||
@ -78,33 +80,22 @@ extern struct simops Simops[];
|
||||
|
||||
#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
|
||||
|
||||
#define RB(x) (*((uint8 *)((x)+State.imem)))
|
||||
#define RB(x) (*((uint8 *)((x)+State.mem)))
|
||||
#define SB(addr,data) ( RB(addr) = (data & 0xff))
|
||||
|
||||
#ifdef WORDS_BIGENDIAN
|
||||
|
||||
#define RW(x) (*((uint16 *)((x)+State.imem)))
|
||||
#define RLW(x) (*((uint32 *)((x)+State.imem)))
|
||||
#define SW(addr,data) RW(addr)=data
|
||||
#define READ_16(x) (*((int16 *)(x)))
|
||||
#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
|
||||
#define READ_64(x) (*((int64 *)(x)))
|
||||
#define WRITE_64(addr,data) (*(int64 *)(addr)=data)
|
||||
uint32 get_word PARAMS ((uint8 *));
|
||||
uint16 get_half PARAMS ((uint8 *));
|
||||
uint8 get_byte PARAMS ((uint8 *));
|
||||
#define RLW(x) (*((uint32 *)((x)+State.mem)))
|
||||
|
||||
#else
|
||||
|
||||
uint32 get_longword PARAMS ((uint8 *));
|
||||
uint16 get_word PARAMS ((uint8 *));
|
||||
int64 get_longlong PARAMS ((uint8 *));
|
||||
void write_word PARAMS ((uint8 *addr, uint16 data));
|
||||
void write_longlong PARAMS ((uint8 *addr, int64 data));
|
||||
uint32 get_word PARAMS ((uint8 *));
|
||||
uint16 get_half PARAMS ((uint8 *));
|
||||
uint8 get_byte PARAMS ((uint8 *));
|
||||
|
||||
#define SW(addr,data) write_word((long)(addr)+State.imem,data)
|
||||
#define RW(x) get_word((long)(x)+State.imem)
|
||||
#define RLW(x) get_longword((long)(x)+State.imem)
|
||||
#define READ_16(x) get_word(x)
|
||||
#define WRITE_16(addr,data) write_word(addr,data)
|
||||
#define READ_64(x) get_longlong(x)
|
||||
#define WRITE_64(addr,data) write_longlong(addr,data)
|
||||
#define RLW(x) get_word((long)(x)+State.mem)
|
||||
|
||||
#endif /* not WORDS_BIGENDIAN */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user