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2002-03-10 Daniel Jacobowitz <drow@mvista.com>
Don Howard <dhoward@redhat.com>
* mips-tdep.c (ST0_FR): Define.
(mips2_fp_compat): New function, temporarily disabled.
(mips_read_fp_register_single): New function.
(mips_read_fp_register_double): New function.
(mips_print_register): Use them.
(do_fp_register_row): Likewise.
This commit is contained in:
Daniel Jacobowitz
parent
3029f9b89c
commit
dd824b049b
@ -1,3 +1,13 @@
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2002-03-10 Daniel Jacobowitz <drow@mvista.com>
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Don Howard <dhoward@redhat.com>
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* mips-tdep.c (ST0_FR): Define.
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(mips2_fp_compat): New function, temporarily disabled.
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(mips_read_fp_register_single): New function.
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(mips_read_fp_register_double): New function.
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(mips_print_register): Use them.
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(do_fp_register_row): Likewise.
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2002-03-09 Andrew Cagney <ac131313@redhat.com>
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* MAINTAINERS: Add Jim Ingham and Klee Dienes to ``write after
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209
gdb/mips-tdep.c
209
gdb/mips-tdep.c
@ -44,6 +44,10 @@
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#include "elf-bfd.h"
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#include "symcat.h"
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/* A useful bit in the CP0 status register (PS_REGNUM). */
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/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
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#define ST0_FR (1 << 26)
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/* The sizes of floating point registers. */
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enum
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@ -174,6 +178,31 @@ mips_saved_regsize (void)
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return 4;
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}
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/* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
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compatiblity mode. A return value of 1 means that we have
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physical 64-bit registers, but should treat them as 32-bit registers. */
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static int
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mips2_fp_compat (void)
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{
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/* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
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meaningful. */
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if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4)
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return 0;
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#if 0
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/* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
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in all the places we deal with FP registers. PR gdb/413. */
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/* Otherwise check the FR bit in the status register - it controls
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the FP compatiblity mode. If it is clear we are in compatibility
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mode. */
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if ((read_register (PS_REGNUM) & ST0_FR) == 0)
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return 1;
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#endif
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return 0;
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}
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/* Indicate that the ABI makes use of double-precision registers
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provided by the FPU (rather than combining pairs of registers to
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form double-precision values). Do not use "TARGET_IS_MIPS64" to
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@ -257,6 +286,9 @@ find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame);
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static CORE_ADDR after_prologue (CORE_ADDR pc,
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mips_extra_func_info_t proc_desc);
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static void mips_read_fp_register_single (int regno, char *rare_buffer);
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static void mips_read_fp_register_double (int regno, char *rare_buffer);
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/* This value is the model of MIPS in use. It is derived from the value
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of the PrID register. */
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@ -2676,6 +2708,104 @@ mips_pop_frame (void)
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}
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}
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/* Floating point register management.
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Background: MIPS1 & 2 fp registers are 32 bits wide. To support
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64bit operations, these early MIPS cpus treat fp register pairs
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(f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
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registers and offer a compatibility mode that emulates the MIPS2 fp
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model. When operating in MIPS2 fp compat mode, later cpu's split
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double precision floats into two 32-bit chunks and store them in
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consecutive fp regs. To display 64-bit floats stored in this
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fashion, we have to combine 32 bits from f0 and 32 bits from f1.
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Throw in user-configurable endianness and you have a real mess.
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The way this works is:
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- If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
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double-precision value will be split across two logical registers.
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The lower-numbered logical register will hold the low-order bits,
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regardless of the processor's endianness.
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- If we are on a 64-bit processor, and we are looking for a
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single-precision value, it will be in the low ordered bits
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of a 64-bit GPR (after mfc1, for example) or a 64-bit register
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save slot in memory.
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- If we are in 64-bit mode, everything is straightforward.
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Note that this code only deals with "live" registers at the top of the
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stack. We will attempt to deal with saved registers later, when
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the raw/cooked register interface is in place. (We need a general
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interface that can deal with dynamic saved register sizes -- fp
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regs could be 32 bits wide in one frame and 64 on the frame above
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and below). */
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/* Copy a 32-bit single-precision value from the current frame
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into rare_buffer. */
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static void
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mips_read_fp_register_single (int regno, char *rare_buffer)
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{
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int raw_size = REGISTER_RAW_SIZE (regno);
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char *raw_buffer = alloca (raw_size);
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if (read_relative_register_raw_bytes (regno, raw_buffer))
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error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
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if (raw_size == 8)
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{
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/* We have a 64-bit value for this register. Find the low-order
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32 bits. */
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int offset;
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if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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offset = 4;
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else
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offset = 0;
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memcpy (rare_buffer, raw_buffer + offset, 4);
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}
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else
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{
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memcpy (rare_buffer, raw_buffer, 4);
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}
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}
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/* Copy a 64-bit double-precision value from the current frame into
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rare_buffer. This may include getting half of it from the next
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register. */
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static void
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mips_read_fp_register_double (int regno, char *rare_buffer)
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{
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int raw_size = REGISTER_RAW_SIZE (regno);
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if (raw_size == 8 && !mips2_fp_compat ())
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{
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/* We have a 64-bit value for this register, and we should use
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all 64 bits. */
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if (read_relative_register_raw_bytes (regno, rare_buffer))
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error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
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}
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else
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{
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if ((regno - FP0_REGNUM) & 1)
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internal_error (__FILE__, __LINE__,
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"mips_read_fp_register_double: bad access to "
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"odd-numbered FP register");
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/* mips_read_fp_register_single will find the correct 32 bits from
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each register. */
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if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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{
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mips_read_fp_register_single (regno, rare_buffer + 4);
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mips_read_fp_register_single (regno + 1, rare_buffer);
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}
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else
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{
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mips_read_fp_register_single (regno, rare_buffer);
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mips_read_fp_register_single (regno + 1, rare_buffer + 4);
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}
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}
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}
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static void
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mips_print_register (int regnum, int all)
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{
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@ -2688,22 +2818,23 @@ mips_print_register (int regnum, int all)
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return;
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}
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/* If an even floating point register, also print as double. */
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/* If we have a actual 32-bit floating point register (or we are in
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32-bit compatibility mode), and the register is even-numbered,
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also print it as a double (spanning two registers). */
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if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
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&& (REGISTER_RAW_SIZE (regnum) == 4
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|| mips2_fp_compat ())
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&& !((regnum - FP0_REGNUM) & 1))
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if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
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{
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char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
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{
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char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
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read_relative_register_raw_bytes (regnum, dbuffer);
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read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE);
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REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer);
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mips_read_fp_register_double (regnum, dbuffer);
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printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
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val_print (builtin_type_double, dbuffer, 0, 0,
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gdb_stdout, 0, 1, 0, Val_pretty_default);
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printf_filtered ("); ");
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}
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printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
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val_print (builtin_type_double, dbuffer, 0, 0,
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gdb_stdout, 0, 1, 0, Val_pretty_default);
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printf_filtered ("); ");
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}
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fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
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/* The problem with printing numeric register names (r26, etc.) is that
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@ -2717,8 +2848,10 @@ mips_print_register (int regnum, int all)
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/* If virtual format is floating, print it that way. */
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if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
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if (FP_REGISTER_DOUBLE)
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{ /* show 8-byte floats as float AND double: */
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if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
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{
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/* We have a meaningful 64-bit value in this register. Show
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it as a 32-bit float and a 64-bit double. */
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int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
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printf_filtered (" (float) ");
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@ -2753,35 +2886,25 @@ mips_print_register (int regnum, int all)
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static int
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do_fp_register_row (int regnum)
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{ /* do values for FP (float) regs */
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char *raw_buffer[2];
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char *dbl_buffer;
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/* use HI and LO to control the order of combining two flt regs */
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int HI = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
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int LO = (TARGET_BYTE_ORDER != BFD_ENDIAN_BIG);
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char *raw_buffer;
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double doub, flt1, flt2; /* doubles extracted from raw hex data */
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int inv1, inv2, inv3;
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raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
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raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
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dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
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raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
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/* Get the data in raw format. */
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if (read_relative_register_raw_bytes (regnum, raw_buffer[HI]))
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error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
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if (REGISTER_RAW_SIZE (regnum) == 4)
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if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
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{
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/* 4-byte registers: we can fit two registers per row. */
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/* Also print every pair of 4-byte regs as an 8-byte double. */
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if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO]))
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error ("can't read register %d (%s)",
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regnum + 1, REGISTER_NAME (regnum + 1));
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/* 4-byte registers: we can fit two registers per row. */
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/* Also print every pair of 4-byte regs as an 8-byte double. */
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mips_read_fp_register_single (regnum, raw_buffer);
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flt1 = unpack_double (builtin_type_float, raw_buffer, &inv1);
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/* copy the two floats into one double, and unpack both */
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memcpy (dbl_buffer, raw_buffer, 2 * REGISTER_RAW_SIZE (FP0_REGNUM));
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flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1);
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flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2);
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doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
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mips_read_fp_register_single (regnum + 1, raw_buffer);
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flt2 = unpack_double (builtin_type_float, raw_buffer, &inv2);
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mips_read_fp_register_double (regnum, raw_buffer);
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doub = unpack_double (builtin_type_double, raw_buffer, &inv3);
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printf_filtered (" %-5s", REGISTER_NAME (regnum));
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if (inv1)
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printf_filtered (": <invalid float>");
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@ -2805,14 +2928,14 @@ do_fp_register_row (int regnum)
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regnum += 2;
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}
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else
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{ /* eight byte registers: print each one as float AND as double. */
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int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
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memcpy (dbl_buffer, raw_buffer[HI], 2 * REGISTER_RAW_SIZE (FP0_REGNUM));
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flt1 = unpack_double (builtin_type_float,
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&raw_buffer[HI][offset], &inv1);
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doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
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{
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/* Eight byte registers: print each one as float AND as double. */
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mips_read_fp_register_single (regnum, raw_buffer);
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flt1 = unpack_double (builtin_type_double, raw_buffer, &inv1);
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mips_read_fp_register_double (regnum, raw_buffer);
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doub = unpack_double (builtin_type_double, raw_buffer, &inv3);
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printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
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if (inv1)
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printf_filtered ("<invalid float>");
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