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* simops.c: Implement the remaining 5, 6 and 7 byte instructions.
Everything except the extended instructions, the loop instructions, trap, rti, and rtm.
This commit is contained in:
Jeff Law
parent
ecb4b5a357
commit
de0dce7c5c
@ -1,5 +1,7 @@
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Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Implement the remaining 5, 6 and 7 byte instructions.
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* simops.c: Implement remaining 4 byte instructions.
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* simops.c: Implement remaining 3 byte instructions.
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@ -157,9 +157,12 @@ void OP_FA000000 ()
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+ SEXT16 (insn & 0xffff)), 4);
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}
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/* mov */
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/* mov (d32,am), dn */
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void OP_FC000000 ()
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{
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) | extension), 4);
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}
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/* mov (d8,sp), dn */
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@ -176,9 +179,11 @@ void OP_FAB40000 ()
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= load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
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}
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/* mov */
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/* mov (d32,sp), dn */
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void OP_FCB40000 ()
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{
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
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}
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/* mov (di,am), dn */
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@ -195,9 +200,11 @@ void OP_300000 ()
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
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}
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/* mov */
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/* mov (abs32), dn */
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void OP_FCA40000 ()
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{
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem ((((insn & 0xffff) << 16) + extension), 4);
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}
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/* mov (am), an */
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@ -223,9 +230,12 @@ void OP_FA200000 ()
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+ SEXT16 (insn & 0xffff)), 4);
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}
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/* mov */
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/* mov (d32,am), an */
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void OP_FC200000 ()
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{
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 4);
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}
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/* mov (d8,sp), an */
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@ -242,12 +252,14 @@ void OP_FAB00000 ()
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= load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
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}
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/* mov */
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/* mov (d32,sp), an */
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void OP_FCB00000 ()
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{
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
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}
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/* mov (di,am), an*/
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/* mov (di,am), an */
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void OP_F380 ()
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{
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State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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@ -261,9 +273,11 @@ void OP_FAA00000 ()
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
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}
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/* mov */
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/* mov (abs32), an */
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void OP_FCA00000 ()
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{
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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= load_mem ((((insn & 0xffff) << 16) + extension), 4);
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}
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/* mov (d8,am), sp */
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@ -297,9 +311,12 @@ void OP_FA100000 ()
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov */
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/* mov dm (d32,an) */
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void OP_FC100000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 4,
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov dm, (d8,sp) */
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@ -316,9 +333,11 @@ void OP_FA910000 ()
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov */
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/* mov dm, (d32,sp) */
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void OP_FC910000 ()
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{
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store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov dm, (di,an) */
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@ -335,9 +354,10 @@ void OP_10000 ()
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store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov */
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/* mov dm, (abs32) */
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void OP_FC810000 ()
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{
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store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov am, (an) */
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@ -355,7 +375,7 @@ void OP_F83000 ()
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State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
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}
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/* mov am (d16,an) */
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/* mov am, (d16,an) */
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void OP_FA300000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
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@ -363,9 +383,12 @@ void OP_FA300000 ()
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov */
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/* mov am, (d32,an) */
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void OP_FC300000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
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+ ((insn & 0xffff) << 16) + extension), 4,
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov am, (d8,sp) */
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@ -382,9 +405,11 @@ void OP_FA900000 ()
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov */
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/* mov am, (d32,sp) */
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void OP_FC900000 ()
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{
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store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov am, (di,an) */
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@ -401,9 +426,10 @@ void OP_FA800000 ()
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store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov */
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/* mov am, (abs32) */
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void OP_FC800000 ()
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{
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store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
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}
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/* mov sp, (d8,an) */
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@ -422,9 +448,13 @@ void OP_2C0000 ()
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
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}
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/* mov */
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/* mov imm32,dn */
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void OP_FCCC0000 ()
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{
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unsigned long value;
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value = (insn & 0xffff) << 16 | extension;
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
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}
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/* mov imm16, an */
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@ -436,7 +466,7 @@ void OP_240000 ()
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
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}
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/* mov imm32, an*/
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/* mov imm32, an */
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void OP_FCDC0000 ()
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{
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unsigned long value;
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@ -468,9 +498,12 @@ void OP_FA400000 ()
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+ SEXT16 (insn & 0xffff)), 1);
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}
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/* movbu */
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/* movbu (d32,am), dn */
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void OP_FC400000 ()
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{
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 1);
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}
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/* movbu (d8,sp), dn */
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@ -487,9 +520,11 @@ void OP_FAB80000 ()
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= load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
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}
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/* movbu */
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/* movbu (d32,sp), dn */
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void OP_FCB80000 ()
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{
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
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}
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/* movbu (di,am), dn */
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@ -506,9 +541,11 @@ void OP_340000 ()
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
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}
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/* movbu */
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/* movbu (abs32), dn */
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void OP_FCA80000 ()
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{
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem ((((insn & 0xffff) << 16) + extension), 1);
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}
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/* movbu dm, (an) */
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@ -530,13 +567,16 @@ void OP_F85000 ()
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void OP_FA500000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ SEXT8 (insn & 0xffff)), 1,
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+ SEXT16 (insn & 0xffff)), 1,
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movbu */
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/* movbu dm, (d32,an) */
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void OP_FC500000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 1,
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movbu dm, (d8,sp) */
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@ -553,9 +593,11 @@ void OP_FA920000 ()
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* movbu */
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/* movbu dm (d32,sp) */
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void OP_FC920000 ()
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{
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store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
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}
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/* movbu dm, (di,an) */
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@ -572,9 +614,10 @@ void OP_20000 ()
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store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movbu */
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/* movbu dm, (abs32) */
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void OP_FC820000 ()
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{
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store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movhu (am), dn */
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@ -600,9 +643,12 @@ void OP_FA600000 ()
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+ SEXT16 (insn & 0xffff)), 2);
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}
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/* movhu */
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/* movhu (d32,am), dn */
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void OP_FC600000 ()
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{
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 2);
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}
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/* movhu (d8,sp) dn */
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@ -619,9 +665,11 @@ void OP_FABC0000 ()
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= load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
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}
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/* movhu */
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/* movhu (d32,sp), dn */
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void OP_FCBC0000 ()
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{
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
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}
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/* movhu (di,am), dn */
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@ -638,9 +686,11 @@ void OP_380000 ()
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
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}
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/* movhu */
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/* movhu (abs32), dn */
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void OP_FCAC0000 ()
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{
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem ((((insn & 0xffff) << 16) + extension), 2);
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}
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/* movhu dm, (an) */
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@ -666,9 +716,12 @@ void OP_FA700000 ()
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movhu */
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/* movhu dm, (d32,an) */
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void OP_FC700000 ()
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{
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store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 2,
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movhu dm,(d8,sp) */
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@ -685,9 +738,11 @@ void OP_FA930000 ()
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movhu */
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/* movhu dm,(d32,sp) */
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void OP_FC930000 ()
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{
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store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movhu dm, (di,an) */
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@ -704,9 +759,10 @@ void OP_30000 ()
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store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* movhu */
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/* movhu dm, (abs32) */
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void OP_FC830000 ()
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{
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store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
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}
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/* ext dn */
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@ -862,7 +918,7 @@ void OP_0 ()
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PSW &= ~(PSW_V | PSW_C | PSW_N);
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}
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/* add dm,dn*/
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/* add dm,dn */
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void OP_E0 ()
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{
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int z, c, n, v;
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@ -906,7 +962,7 @@ void OP_F160 ()
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add am, dn*/
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/* add am, dn */
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void OP_F150 ()
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{
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int z, c, n, v;
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@ -1082,7 +1138,7 @@ void OP_FCD00000 ()
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add imm8, sp*/
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/* add imm8, sp */
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void OP_F8FE00 ()
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{
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int z, c, n, v;
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@ -1126,7 +1182,7 @@ void OP_FAFE0000 ()
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm32, sp */
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void OP_FCFE0000 ()
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{
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int z, c, n, v;
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@ -1148,7 +1204,7 @@ void OP_FCFE0000 ()
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* addc */
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/* addc dm,dn */
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void OP_F140 ()
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{
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int z, c, n, v;
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@ -1258,7 +1314,7 @@ void OP_F130 ()
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State.regs[REG_A0 + (insn & 0x3)] = value;
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}
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/* sub */
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/* sub imm32, dn */
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void OP_FCC40000 ()
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{
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int z, c, n, v;
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@ -1280,7 +1336,7 @@ void OP_FCC40000 ()
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State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
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}
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/* sub */
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/* sub imm32, an */
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void OP_FCD40000 ()
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{
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int z, c, n, v;
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@ -1302,7 +1358,7 @@ void OP_FCD40000 ()
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State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
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}
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/* subc */
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/* subc dm, dn */
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void OP_F180 ()
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{
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int z, c, n, v;
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@ -1324,7 +1380,7 @@ void OP_F180 ()
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State.regs[REG_D0 + (insn & 0x3)] = value;
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}
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/* mul */
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/* mul dm, dn */
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void OP_F240 ()
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{
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unsigned long long temp;
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@ -1340,7 +1396,7 @@ void OP_F240 ()
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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/* mulu */
|
||||
/* mulu dm, dn */
|
||||
void OP_F250 ()
|
||||
{
|
||||
unsigned long long temp;
|
||||
@ -1356,7 +1412,7 @@ void OP_F250 ()
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* div */
|
||||
/* div dm, dn */
|
||||
void OP_F260 ()
|
||||
{
|
||||
long long temp;
|
||||
@ -1377,7 +1433,7 @@ void OP_F260 ()
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* divu */
|
||||
/* divu dm, dn */
|
||||
void OP_F270 ()
|
||||
{
|
||||
unsigned long long temp;
|
||||
@ -1662,9 +1718,17 @@ void OP_FAE00000 ()
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* and */
|
||||
/* and imm32, dn */
|
||||
void OP_FCE00000 ()
|
||||
{
|
||||
int n, z;
|
||||
|
||||
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
||||
&= ((insn & 0xffff) << 16 | extension);
|
||||
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
||||
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* and imm16, psw */
|
||||
@ -1709,9 +1773,17 @@ void OP_FAE40000 ()
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* or */
|
||||
/* or imm32, dn */
|
||||
void OP_FCE40000 ()
|
||||
{
|
||||
int n, z;
|
||||
|
||||
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
||||
|= ((insn & 0xffff) << 16 | extension);
|
||||
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
||||
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* or imm16,psw */
|
||||
@ -1744,12 +1816,20 @@ void OP_FAE80000 ()
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* xor */
|
||||
/* xor imm32, dn */
|
||||
void OP_FCE80000 ()
|
||||
{
|
||||
int n, z;
|
||||
|
||||
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
||||
^= ((insn & 0xffff) << 16 | extension);
|
||||
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
||||
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
||||
}
|
||||
|
||||
/* not */
|
||||
/* not dn */
|
||||
void OP_F230 ()
|
||||
{
|
||||
int n, z;
|
||||
@ -1789,14 +1869,32 @@ void OP_FAEC0000 ()
|
||||
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
||||
}
|
||||
|
||||
/* btst */
|
||||
/* btst imm32, dn */
|
||||
void OP_FCEC0000 ()
|
||||
{
|
||||
unsigned long temp;
|
||||
int z, n;
|
||||
|
||||
temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
||||
temp &= ((insn & 0xffff) << 16 | extension);
|
||||
n = (temp & 0x80000000) != 0;
|
||||
z = (temp == 0);
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
||||
}
|
||||
|
||||
/* btst */
|
||||
/* btst imm8,(abs32) */
|
||||
void OP_FE020000 ()
|
||||
{
|
||||
unsigned long temp;
|
||||
int n, z;
|
||||
|
||||
temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
|
||||
temp &= (extension & 0xff);
|
||||
n = (temp & 0x80000000) != 0;
|
||||
z = (temp == 0);
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
||||
}
|
||||
|
||||
/* btst imm8,(d8,an) */
|
||||
@ -1828,9 +1926,18 @@ void OP_F080 ()
|
||||
PSW |= (z ? PSW_Z : 0);
|
||||
}
|
||||
|
||||
/* bset */
|
||||
/* bset imm8, (abs32) */
|
||||
void OP_FE000000 ()
|
||||
{
|
||||
unsigned long temp;
|
||||
int z;
|
||||
|
||||
temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
|
||||
z = (temp & (extension & 0xff)) == 0;
|
||||
temp |= (extension & 0xff);
|
||||
store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= (z ? PSW_Z : 0);
|
||||
}
|
||||
|
||||
/* bset imm8,(d8,an) */
|
||||
@ -1862,9 +1969,18 @@ void OP_F090 ()
|
||||
PSW |= (z ? PSW_Z : 0);
|
||||
}
|
||||
|
||||
/* bclr */
|
||||
/* bclr imm8, (abs32) */
|
||||
void OP_FE010000 ()
|
||||
{
|
||||
unsigned long temp;
|
||||
int z;
|
||||
|
||||
temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
|
||||
z = (temp & (extension & 0xff)) == 0;
|
||||
temp = ~temp & (extension & 0xff);
|
||||
store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= (z ? PSW_Z : 0);
|
||||
}
|
||||
|
||||
/* bclr imm8,(d8,an) */
|
||||
@ -2417,7 +2533,7 @@ void OP_FCFF0000 ()
|
||||
State.pc += (((insn & 0xffff) << 16) | extension) - 6;
|
||||
}
|
||||
|
||||
/* ret */
|
||||
/* ret reg_list, imm8 */
|
||||
void OP_DF0000 ()
|
||||
{
|
||||
unsigned int sp;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user