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* simops.c: Treat both operands as signed values for

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"div" instruction.
Fixes another dozen c-torture execution failures.
This commit is contained in:
Jeff Law 1996-12-04 05:00:49 +00:00
parent b61802e7cb
commit e4e1302293
2 changed files with 13 additions and 2 deletions
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11
sim/mn10300/ChangeLog
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@ -1,5 +1,16 @@
Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Treat both operands as signed values for
"div" instruction.
* simops.c: Fix simulation of division instructions.
Fix typos/thinkos in several "cmp" and "sub" instructions.
Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix carry bit handling in "sub" and "cmp"
instructions.
* simops.c: Fix "mov imm8,an" and "mov imm16,dn".
Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)

4
sim/mn10300/simops.c
View File

@ -1421,8 +1421,8 @@ void OP_F260 ()
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[REG_D0 + (insn & 0x3)];
State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);