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ARM process record: VMOV
ARM process record gets the wrong register number for VMOV (from core register to single-precision register). That is, we should record the D register rather than the S pseudo register. The patch also removes the condition "bit (arm_insn_r->arm_insn, 20)" check, which has been checked above. It fixes the following internal error, (gdb) PASS: gdb.reverse/finish-precsave.exp: BP at end of main continue^M Continuing.^M ../../binutils-gdb/gdb/regcache.c:649: internal-error: regcache_raw_read: Assertion `regnum >= 0 && regnum < regcache->descr->nr_raw_registers' failed.^M A problem internal to GDB has been detected,FAIL: gdb.reverse/finish-precsave.exp: run to end of main (GDB internal error) gdb: 2016-03-04 Yao Qi <yao.qi@linaro.org> * arm-tdep.c (arm_record_vdata_transfer_insn): Simplify the condition check. Record the right D register number.
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@ -1,3 +1,8 @@
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2016-03-04 Yao Qi <yao.qi@linaro.org>
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* arm-tdep.c (arm_record_vdata_transfer_insn): Simplify the
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condition check. Record the right D register number.
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2016-03-04 Yao Qi <yao.qi@linaro.org>
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* arm-tdep.c (arm_record_extension_space): Remove code
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@ -10800,12 +10800,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
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/* Handle VMOV instruction. */
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if (bits_a == 0x00)
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{
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if (bit (arm_insn_r->arm_insn, 20))
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record_buf[0] = reg_t;
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else
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record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
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(reg_v << 1));
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record_buf[0] = reg_t;
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arm_insn_r->reg_rec_count = 1;
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}
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/* Handle VMRS instruction. */
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@ -10823,11 +10818,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
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/* Handle VMOV instruction. */
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if (bits_a == 0x00)
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{
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if (bit (arm_insn_r->arm_insn, 20))
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record_buf[0] = reg_t;
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else
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record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
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(reg_v << 1));
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record_buf[0] = ARM_D0_REGNUM + reg_v;
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arm_insn_r->reg_rec_count = 1;
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}
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