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* gas/config/tc-arm.c (arm_ext_v6z): Remove.

Browse Source 
(arm_ext_sec): New variable.
	(do_t_smc): In Thumb state SMC requires v7-A.
	(insns): Make SMC depend on Security Extensions.
	(arm_cpus): All -mcpu=cortex-a* options have the Security Extensions.
	(arm_extensions): Add 'sec' extension.
	(cpu_arch_ver): Reorder.
	(aeabi_set_public_attributes): Emit Tag_Virtualization_use as
	appropriate.
	* gas/doc/c-arm.texi: Document Security Extensions.
	* gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions..
	* gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test.
	* gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions.
	* gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise.
	* gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise.
	* gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise.
	* gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test.
	* gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions.
	* gas/testsuite/gas/arm/thumb32.d: Likewise.
	* gas/testsuite/gas/arm/thumb32.s: Likewise.
	* include/opcode/arm.h (ARM_EXT_V6Z): Remove.
	(ARM_EXT_SEC): New define.
	(ARM_AEXT_V6Z): Use Security Extensions.
	(ARM_AEXT_V6ZK): Likeiwse.
	(ARM_AEXT_V6ZT2): Likewise.
	(ARM_AEXT_V6ZKT2): Likewise.
	(ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions.
	(ARM_ARCH_V7A_SEC): New define.
	(ARM_ARCH_V7A_MP): Rename...
	(ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions.
	* ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions.
	* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
	* opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions.
	(thumb32_opcodes): Likewise.
This commit is contained in:
Matthew Gretton-Dann 2010-09-23 15:26:24 +00:00
parent 60e5ef9f19
commit f4c65163c7
22 changed files with 135 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
gas/ChangeLog
View File

@ -1,3 +1,16 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (arm_ext_v6z): Remove.
(arm_ext_sec): New variable.
(do_t_smc): In Thumb state SMC requires v7-A.
(insns): Make SMC depend on Security Extensions.
(arm_cpus): All -mcpu=cortex-a* options have the Security Extensions.
(arm_extensions): Add 'sec' extension.
(cpu_arch_ver): Reorder.
(aeabi_set_public_attributes): Emit Tag_Virtualization_use as
appropriate.
* doc/c-arm.texi: Document Security Extensions.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (arm_ext_mp): Add.

30
gas/config/tc-arm.c
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@ -184,7 +184,6 @@ static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
@ -198,6 +197,7 @@ static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
static const arm_feature_set arm_ext_m =
ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0);
static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
static const arm_feature_set arm_arch_any = ARM_ANY;
static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
@ -11357,6 +11357,8 @@ static void
do_t_smc (void)
{
unsigned int value = inst.reloc.exp.X_add_number;
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
_("SMC is not permitted on this architecture"));
constraint (inst.reloc.exp.X_op != O_constant,
_("expression too complex"));
inst.reloc.type = BFD_RELOC_UNUSED;
@ -17049,12 +17051,16 @@ static const struct asm_opcode insns[] =
TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v6z
#define ARM_VARIANT & arm_ext_sec
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_sec
TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v6t2
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v6t2
TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
@ -22381,14 +22387,18 @@ static const struct arm_cpu_option_table arm_cpus[] =
{"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
{"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
{"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
{"cortex-a5", ARM_ARCH_V7A_MP, FPU_NONE, "Cortex-A5"},
{"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3
{"cortex-a5", ARM_ARCH_V7A_MP_SEC,
FPU_NONE, "Cortex-A5"},
{"cortex-a8", ARM_ARCH_V7A_SEC,
ARM_FEATURE (0, FPU_VFP_V3
| FPU_NEON_EXT_V1),
"Cortex-A8"},
{"cortex-a9", ARM_ARCH_V7A_MP, ARM_FEATURE (0, FPU_VFP_V3
{"cortex-a9", ARM_ARCH_V7A_MP_SEC,
ARM_FEATURE (0, FPU_VFP_V3
| FPU_NEON_EXT_V1),
"Cortex-A9"},
{"cortex-a15", ARM_ARCH_V7A_MP, FPU_ARCH_NEON_VFP_V4,
{"cortex-a15", ARM_ARCH_V7A_MP_SEC,
FPU_ARCH_NEON_VFP_V4,
"Cortex-A15"},
{"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
{"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
@ -22479,6 +22489,8 @@ static const struct arm_option_extension_value_table arm_extensions[] =
{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
{"mp", ARM_FEATURE (ARM_EXT_MP, 0),
ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
{"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
{"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
{NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
};
@ -22999,8 +23011,8 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
{4, ARM_ARCH_V5TE},
{5, ARM_ARCH_V5TEJ},
{6, ARM_ARCH_V6},
{7, ARM_ARCH_V6Z},
{9, ARM_ARCH_V6K},
{7, ARM_ARCH_V6Z},
{11, ARM_ARCH_V6M},
{8, ARM_ARCH_V6T2},
{10, ARM_ARCH_V7A},
@ -23161,6 +23173,10 @@ aeabi_set_public_attributes (void)
/* Tag_MP_extension_use. */
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
aeabi_set_attribute_int (Tag_MPextension_use, 1);
/* Tag Virtualization_use. */
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
aeabi_set_attribute_int (Tag_Virtualization_use, 1);
}
/* Add the default contents for the .ARM.attributes section. */

1
gas/doc/c-arm.texi
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@ -153,6 +153,7 @@ The following extensions are currently supported:
@code{iwmmxt2},
@code{maverick},
@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
@code{sec} (Security Extensions for v6K and v7-A architectures),
and
@code{xscale}.

13
gas/testsuite/ChangeLog
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@ -1,3 +1,16 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/attr-march-all.d: Update for Security Extensions..
* gas/arm/attr-march-armv6k+sec.d: New test.
* gas/arm/attr-march-armv6z.d: Update for Security Extensions.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: New test.
* gas/arm/attr-mcpu.d: Update for Security Extensions.
* gas/arm/thumb32.d: Likewise.
* gas/arm/thumb32.s: Likewise.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/arch7a-mp.d: Add.

1
gas/testsuite/gas/arm/attr-cpu-directive.d
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@ -13,3 +13,4 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

1
gas/testsuite/gas/arm/attr-march-all.d
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@ -13,3 +13,4 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_MPextension_use: Allowed
Tag_Virtualization_use: TrustZone

15
gas/testsuite/gas/arm/attr-march-armv6k+sec.d Normal file
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@ -0,0 +1,15 @@
# name: attributes for -march=armv6k+sec
# source: blank.s
# as: -march=armv6k+sec
# readelf: -A
# This test is only valid on EABI based ports.
# target: *-*-*eabi
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "6K"
Tag_CPU_arch: v6KZ
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

1
gas/testsuite/gas/arm/attr-march-armv6z.d
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@ -12,3 +12,4 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

3
gas/testsuite/gas/arm/attr-march-armv6zk.d
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@ -8,7 +8,8 @@
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "6ZK"
Tag_CPU_arch: v6K
Tag_CPU_arch: v6KZ
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

1
gas/testsuite/gas/arm/attr-march-armv6zkt2.d
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@ -12,3 +12,4 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

1
gas/testsuite/gas/arm/attr-march-armv6zt2.d
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@ -12,3 +12,4 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

16
gas/testsuite/gas/arm/attr-march-armv7-a+sec.d Normal file
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@ -0,0 +1,16 @@
# name: attributes for -march=armv7-a+sec
# source: blank.s
# as: -march=armv7-a+sec
# readelf: -A
# This test is only valid on EABI based ports.
# target: *-*-*eabi
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "7-A"
Tag_CPU_arch: v7
Tag_CPU_arch_profile: Application
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

1
gas/testsuite/gas/arm/attr-mcpu.d
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@ -15,3 +15,4 @@ File Attributes
Tag_FP_arch: VFPv3
Tag_Advanced_SIMD_arch: NEONv1
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

2
gas/testsuite/gas/arm/thumb32.d
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@ -1,5 +1,5 @@
# name: 32-bit Thumb instructions
# as: -march=armv6kt2
# as: -march=armv6zkt2
# objdump: -dr --prefix-addresses --show-raw-insn
# The arm-aout and arm-pe ports do not support Thumb branch relocations.
# not-target: *-*-*aout* *-*-pe

2
gas/testsuite/gas/arm/thumb32.s
View File

@ -631,6 +631,8 @@ rrx:
rrx r1, r2
rrxs r3, r4
.arch armv7-a
.arch_extension sec
smc:
smc #0
smc #0xabcd

13
include/ChangeLog
View File

@ -1,3 +1,16 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm.h (ARM_EXT_V6Z): Remove.
(ARM_EXT_SEC): New define.
(ARM_AEXT_V6Z): Use Security Extensions.
(ARM_AEXT_V6ZK): Likeiwse.
(ARM_AEXT_V6ZT2): Likewise.
(ARM_AEXT_V6ZKT2): Likewise.
(ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions.
(ARM_ARCH_V7A_SEC): New define.
(ARM_ARCH_V7A_MP): Rename...
(ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions.
2010-09-09 Jakub Jelinek <jakub@redhat.com>
* dwarf2.h (DW_OP_GNU_implicit_pointer): New.

20
include/opcode/arm.h
View File

@ -33,7 +33,7 @@
#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
#define ARM_EXT_V6 0x00001000 /* ARM V6. */
#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
/* 0x00004000 Was ARM V6Z. */
#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
#define ARM_EXT_DIV 0x00010000 /* Integer division. */
/* The 'M' in Arm V7M stands for Microcontroller.
@ -50,6 +50,7 @@
#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
not in v7-M. */
#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@ -96,15 +97,15 @@
#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
| ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
| ARM_EXT_V6_DSP )
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
@ -210,7 +211,12 @@
#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
#define ARM_ARCH_V7A_MP ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP, 0)
/* v7-a+sec. */
#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
/* v7-a+mp+sec. */
#define ARM_ARCH_V7A_MP_SEC \
ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
0)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and

5
ld/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* ld-arm/attr-merge-6.attr: Update for Security Extensions.
* ld-arm/attr-merge-7.attr: Likewise.
2010-09-23 Alan Modra <amodra@gmail.com>
* ld-elf/elf.exp: Don't run --gc-sections tls var test on v850.

1
ld/testsuite/ld-arm/attr-merge-6.attr
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@ -7,3 +7,4 @@ File Attributes
Tag_THUMB_ISA_use: Thumb-2
Tag_MPextension_use: Allowed
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

1
ld/testsuite/ld-arm/attr-merge-7.attr
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@ -7,3 +7,4 @@ File Attributes
Tag_THUMB_ISA_use: Thumb-2
Tag_MPextension_use: Allowed
Tag_DIV_use: Not allowed
Tag_Virtualization_use: TrustZone

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): SMC implies Security Extensions.
(thumb32_opcodes): Likewise.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): Add support for pldw.

8
opcodes/arm-dis.c
View File

@ -853,8 +853,8 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
{ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
/* ARM V6Z instructions. */
{ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
/* ARM Security extension instructions. */
{ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
/* ARM V6K instructions. */
{ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
@ -1359,6 +1359,9 @@ static const struct opcode32 thumb32_opcodes[] =
/* MP Extension instructions. */
{ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
/* Security extension instructions. */
{ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
/* Instructions defined in the basic V6T2 set. */
{ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
@ -1480,7 +1483,6 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
{ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
{ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
{ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
{ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
{ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
{ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},