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Add .d32 encoding suffix.
gas/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (_i386_insn): Add disp32_encoding. (md_assemble): Don't call optimize_disp if disp32_encoding is set. (parse_insn): Support .d32 to force 32bit displacement. (output_branch): Use BIG if disp32_encoding is set. * doc/c-i386.texi: Document .d32 encoding suffix. gas/testsuite/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/disp32.d: New. * gas/i386/disp32.s: Likewise. * gas/i386/x86-64-disp32.d: Likewise. * gas/i386/x86-64-disp32.s: Likewise. * gas/i386/i386.exp: Run disp32 and x86-64-disp32.
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H.J. Lu
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@ -1,3 +1,13 @@
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2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (_i386_insn): Add disp32_encoding.
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(md_assemble): Don't call optimize_disp if disp32_encoding is
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set.
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(parse_insn): Support .d32 to force 32bit displacement.
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(output_branch): Use BIG if disp32_encoding is set.
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* doc/c-i386.texi: Document .d32 encoding suffix.
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2010-10-11 Steve Kilbane <steve.kilbane@analog.com>
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* config/bfin-lex.l (FLAGS): New state.
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@ -277,6 +277,9 @@ struct _i386_insn
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/* Swap operand in encoding. */
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unsigned int swap_operand;
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/* Force 32bit displacement in encoding. */
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unsigned int disp32_encoding;
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/* Error message. */
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enum i386_error error;
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};
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@ -2982,6 +2985,7 @@ md_assemble (char *line)
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/* Don't optimize displacement for movabs since it only takes 64bit
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displacement. */
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if (i.disp_operands
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&& !i.disp32_encoding
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&& (flag_code != CODE_64BIT
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|| strcmp (mnemonic, "movabs") != 0))
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optimize_disp ();
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@ -3256,9 +3260,15 @@ parse_insn (char *line, char *mnemonic)
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if (!current_templates)
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{
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/* Check if we should swap operand in encoding. */
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/* Check if we should swap operand or force 32bit displacement in
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encoding. */
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if (mnem_p - 2 == dot_p && dot_p[1] == 's')
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i.swap_operand = 1;
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else if (mnem_p - 4 == dot_p
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&& dot_p[1] == 'd'
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&& dot_p[2] == '3'
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&& dot_p[3] == '2')
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i.disp32_encoding = 1;
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else
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goto check_suffix;
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mnem_p = dot_p;
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@ -5691,15 +5701,15 @@ static void
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output_branch (void)
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{
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char *p;
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int size;
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int code16;
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int prefix;
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relax_substateT subtype;
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symbolS *sym;
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offsetT off;
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code16 = 0;
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if (flag_code == CODE_16BIT)
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code16 = CODE16;
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code16 = flag_code == CODE_16BIT ? CODE16 : 0;
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size = i.disp32_encoding ? BIG : SMALL;
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prefix = 0;
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if (i.prefix[DATA_PREFIX] != 0)
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@ -5742,11 +5752,11 @@ output_branch (void)
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*p = i.tm.base_opcode;
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if ((unsigned char) *p == JUMP_PC_RELATIVE)
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subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
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subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
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else if (cpu_arch_flags.bitfield.cpui386)
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subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
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subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
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else
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subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
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subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
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subtype |= code16;
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sym = i.op[0].disps->X_add_symbol;
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@ -394,7 +394,8 @@ quadruple word).
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Different encoding options can be specified via optional mnemonic
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suffix. @samp{.s} suffix swaps 2 register operands in encoding when
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moving from one register to another.
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moving from one register to another. @samp{.d32} suffix forces 32bit
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displacement in encoding.
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@cindex conversion instructions, i386
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@cindex i386 conversion instructions
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@ -1,3 +1,12 @@
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2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/disp32.d: New.
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* gas/i386/disp32.s: Likewise.
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* gas/i386/x86-64-disp32.d: Likewise.
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* gas/i386/x86-64-disp32.s: Likewise.
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* gas/i386/i386.exp: Run disp32 and x86-64-disp32.
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2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* gas/s390/zarch-z196.d: Adjust the load/store on condition
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19
gas/testsuite/gas/i386/disp32.d
Normal file
19
gas/testsuite/gas/i386/disp32.d
Normal file
@ -0,0 +1,19 @@
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#as:
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#objdump: -drw
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#name: i386 32bit displacement
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo-0x10>:
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[ ]*[a-f0-9]+: 8b 58 03 mov 0x3\(%eax\),%ebx
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[ ]*[a-f0-9]+: 8b 98 03 00 00 00 mov 0x3\(%eax\),%ebx
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[ ]*[a-f0-9]+: eb 05 jmp 10 <foo>
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmp 10 <foo>
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0+10 <foo>:
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[ ]*[a-f0-9]+: 89 58 03 mov %ebx,0x3\(%eax\)
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[ ]*[a-f0-9]+: 89 98 03 00 00 00 mov %ebx,0x3\(%eax\)
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#pass
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11
gas/testsuite/gas/i386/disp32.s
Normal file
11
gas/testsuite/gas/i386/disp32.s
Normal file
@ -0,0 +1,11 @@
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.text
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mov 3(%eax),%ebx
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mov.d32 3(%eax),%ebx
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jmp foo
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jmp.d32 foo
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foo:
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.intel_syntax noprefix
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mov DWORD PTR [eax+3], ebx
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mov.d32 DWORD PTR [eax+3], ebx
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@ -49,6 +49,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "sib-intel"
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run_dump_test "disp"
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run_dump_test "disp-intel"
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run_dump_test "disp32"
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run_dump_test "vmx"
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run_dump_test "smx"
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run_dump_test "suffix"
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@ -323,6 +324,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-sib-intel"
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run_dump_test "x86-64-disp"
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run_dump_test "x86-64-disp-intel"
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run_dump_test "x86-64-disp32"
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run_dump_test "rexw"
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run_dump_test "x86-64-fxsave"
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run_dump_test "x86-64-fxsave-intel"
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19
gas/testsuite/gas/i386/x86-64-disp32.d
Normal file
19
gas/testsuite/gas/i386/x86-64-disp32.d
Normal file
@ -0,0 +1,19 @@
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#as:
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#objdump: -drw
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#name: x86-64 32bit displacement
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo-0x10>:
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[ ]*[a-f0-9]+: 8b 58 03 mov 0x3\(%rax\),%ebx
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[ ]*[a-f0-9]+: 8b 98 03 00 00 00 mov 0x3\(%rax\),%ebx
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[ ]*[a-f0-9]+: eb 05 jmp 10 <foo>
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[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 10 <foo>
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0+10 <foo>:
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[ ]*[a-f0-9]+: 89 58 03 mov %ebx,0x3\(%rax\)
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[ ]*[a-f0-9]+: 89 98 03 00 00 00 mov %ebx,0x3\(%rax\)
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#pass
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11
gas/testsuite/gas/i386/x86-64-disp32.s
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11
gas/testsuite/gas/i386/x86-64-disp32.s
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@ -0,0 +1,11 @@
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.text
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mov 3(%rax),%ebx
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mov.d32 3(%rax),%ebx
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jmp foo
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jmp.d32 foo
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foo:
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.intel_syntax noprefix
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mov DWORD PTR [rax+3], ebx
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mov.d32 DWORD PTR [rax+3], ebx
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