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opcodes/

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2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

gas/testsuite/

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* gas/aarch64/int-insns.d: Update.
	* gas/aarch64/mov.d: Update.
	* gas/aarch64/reloc-insn.d: Update.

ld/testsuite/

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to
	the objdump directive.
	* ld-aarch64/emit-relocs-266.d: Ditto.
	* ld-aarch64/emit-relocs-268.d: Ditto.
	* ld-aarch64/emit-relocs-269.d: Ditto.
	* ld-aarch64/emit-relocs-270.d: Ditto.
	* ld-aarch64/emit-relocs-271.d: Ditto.
	* ld-aarch64/emit-relocs-272.d: Ditto.
This commit is contained in:
Yufeng Zhang 2013-01-04 14:59:33 +00:00
parent a32c3ff848
commit fb098a1efc
15 changed files with 86 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gas/testsuite/ChangeLog
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@ -1,6 +1,12 @@
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/system.d: Update.
* gas/aarch64/int-insns.d: Update.
* gas/aarch64/mov.d: Update.
* gas/aarch64/reloc-insn.d: Update.
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/system.d: Update.
2013-01-02 Nick Clifton <nickc@redhat.com>

24
gas/testsuite/gas/aarch64/int-insns.d
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@ -37,18 +37,18 @@ Disassembly of section .text:
68: 8b430441 add x1, x2, x3, lsr #1
6c: 91001ca5 add x5, x5, #0x7
70: 71000421 subs w1, w1, #0x1
74: d2800c82 movz x2, #0x64
78: d2800c82 movz x2, #0x64
7c: d2800c82 movz x2, #0x64
80: d2a00c82 movz x2, #0x64, lsl #16
84: d2a00c82 movz x2, #0x64, lsl #16
88: d2c00c82 movz x2, #0x64, lsl #32
8c: d2c00c82 movz x2, #0x64, lsl #32
90: d2e00c82 movz x2, #0x64, lsl #48
94: d2e00c82 movz x2, #0x64, lsl #48
98: 52800c81 movz w1, #0x64
9c: 52800c81 movz w1, #0x64
a0: 52a00c81 movz w1, #0x64, lsl #16
74: d2800c82 mov x2, #0x64 // #100
78: d2800c82 mov x2, #0x64 // #100
7c: d2800c82 mov x2, #0x64 // #100
80: d2a00c82 mov x2, #0x640000 // #6553600
84: d2a00c82 mov x2, #0x640000 // #6553600
88: d2c00c82 mov x2, #0x6400000000 // #429496729600
8c: d2c00c82 mov x2, #0x6400000000 // #429496729600
90: d2e00c82 mov x2, #0x64000000000000 // #28147497671065600
94: d2e00c82 mov x2, #0x64000000000000 // #28147497671065600
98: 52800c81 mov w1, #0x64 // #100
9c: 52800c81 mov w1, #0x64 // #100
a0: 52a00c81 mov w1, #0x640000 // #6553600
a4: 8a030041 and x1, x2, x3
a8: 0a0f015e and w30, w10, w15
ac: 12000041 and w1, w2, #0x1

16
gas/testsuite/gas/aarch64/mov.d
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@ -13,14 +13,14 @@ Disassembly of section \.text:
14: 910003ff mov sp, sp
18: aa0f03e7 mov x7, x15
1c: 2a0f03e7 mov w7, w15
20: 52800b01 movz w1, #0x58
24: 12800000 movn w0, #0x0
28: b2607fe0 orr x0, xzr, #0xffffffff00000000
2c: b2400fff orr sp, xzr, #0xf
30: 32000fff orr wsp, wzr, #0xf
34: d28001ff movz xzr, #0xf
38: 528001ff movz wzr, #0xf
20: 52800b01 mov w1, #0x58 // #88
24: 12800000 mov w0, #0xffffffff // #-1
28: b2607fe0 mov x0, #0xffffffff00000000 // #-4294967296
2c: b2400fff mov sp, #0xf // #15
30: 32000fff mov wsp, #0xf // #15
34: d28001ff mov xzr, #0xf // #15
38: 528001ff mov wzr, #0xf // #15
3c: 0e1c3de7 mov w7, v15\.s\[3\]
40: 4e183fef mov x15, v31\.d\[1\]
44: d2801fe0 movz x0, #0xff
44: d2801fe0 mov x0, #0xff // #255
48: 320de400 orr w0, w0, #0x99999999

17
gas/testsuite/gas/aarch64/reloc-insn.d
View File

@ -5,13 +5,13 @@
Disassembly of section \.text:
0000000000000000 <.*>:
0: d281ffe0 movz x0, #0xfff
4: 9280ffe0 movn x0, #0x7ff
8: d2a24681 movz x1, #0x1234, lsl #16
0: d281ffe0 mov x0, #0xfff // #4095
4: 9280ffe0 mov x0, #0xfffffffffffff800 // #-2048
8: d2a24681 mov x1, #0x12340000 // #305397760
c: f28acf01 movk x1, #0x5678
10: 92a00001 movn x1, #0x0, lsl #16
14: f29f0001 movk x1, #0xf800
18: d2d55761 movz x1, #0xaabb, lsl #32
18: d2d55761 mov x1, #0xaabb00000000 // #187720135606272
1c: f2b99ba1 movk x1, #0xccdd, lsl #16
20: f29ddfe1 movk x1, #0xeeff
24: d2c00001 movz x1, #0x0, lsl #32
@ -29,11 +29,11 @@ Disassembly of section \.text:
3c: 92c00001 movn x1, #0x0, lsl #32
40: f2bfffe1 movk x1, #0xffff, lsl #16
44: f29f0001 movk x1, #0xf800
48: d2ffffe1 movz x1, #0xffff, lsl #48
48: d2ffffe1 mov x1, #0xffff000000000000 // #-281474976710656
4c: f2dfffe1 movk x1, #0xffff, lsl #32
50: f2bfffe1 movk x1, #0xffff, lsl #16
54: f29f0001 movk x1, #0xf800
58: d2ffdb81 movz x1, #0xfedc, lsl #48
58: d2ffdb81 mov x1, #0xfedc000000000000 // #-82190693199511552
5c: f2d75301 movk x1, #0xba98, lsl #32
60: f2aeca81 movk x1, #0x7654, lsl #16
64: f2864201 movk x1, #0x3210
@ -121,11 +121,11 @@ Disassembly of section \.text:
11c: 9400001f bl 198 <lab>
120: 94000000 bl 0 <xlab>
120: R_AARCH64_CALL26 xlab
124: d2e24680 movz x0, #0x1234, lsl #48
124: d2e24680 mov x0, #0x1234000000000000 // #1311673391471656960
128: f2cacf00 movk x0, #0x5678, lsl #32
12c: f2b35780 movk x0, #0x9abc, lsl #16
130: f29bde00 movk x0, #0xdef0
134: d2ffdb80 movz x0, #0xfedc, lsl #48
134: d2ffdb80 mov x0, #0xfedc000000000000 // #-82190693199511552
138: f2d75300 movk x0, #0xba98, lsl #32
13c: f2aeca80 movk x0, #0x7654, lsl #16
140: f2864200 movk x0, #0x3210
@ -156,6 +156,5 @@ Disassembly of section \.text:
18c: 39400001 ldrb w1, \[x0\]
190: d65f03c0 ret
0000000000000194 <llit>:
194: deadf00d \.word 0xdeadf00d

11
ld/testsuite/ChangeLog
View File

@ -1,3 +1,14 @@
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to
the objdump directive.
* ld-aarch64/emit-relocs-266.d: Ditto.
* ld-aarch64/emit-relocs-268.d: Ditto.
* ld-aarch64/emit-relocs-269.d: Ditto.
* ld-aarch64/emit-relocs-270.d: Ditto.
* ld-aarch64/emit-relocs-271.d: Ditto.
* ld-aarch64/emit-relocs-272.d: Ditto.
For older changes see ChangeLog-2012
Copyright (C) 2013 Free Software Foundation, Inc.

2
ld/testsuite/ld-aarch64/emit-relocs-264.d
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@ -1,6 +1,6 @@
#source: emit-relocs-264.s
#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0
+10004: 92400000 and x0, x0, #0x1

2
ld/testsuite/ld-aarch64/emit-relocs-266.d
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@ -1,6 +1,6 @@
#source: emit-relocs-266.s
#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0
+10004: 92400000 and x0, x0, #0x1

2
ld/testsuite/ld-aarch64/emit-relocs-268.d
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@ -1,6 +1,6 @@
#source: emit-relocs-268.s
#ld: -T relocs.ld --defsym tempy=0x63001000 --defsym tempy2=0x4500000000 --defsym tempy3=0x1234567812345 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0
+10004: 92400000 and x0, x0, #0x1

2
ld/testsuite/ld-aarch64/emit-relocs-269.d
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@ -1,6 +1,6 @@
#source: emit-relocs-269.s
#ld: -T relocs.ld --defsym tempy=0x6300100100100100 --defsym tempy2=0xf00df00df00df00d --defsym tempy3=0x1234567812345 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0
+10004: 92400000 and x0, x0, #0x1

2
ld/testsuite/ld-aarch64/emit-relocs-270.d
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@ -1,6 +1,6 @@
#source: emit-relocs-270.s
#ld: -T relocs.ld --defsym tempy=0x1012 --defsym tempy2=0x4500 --defsym tempy3=-292 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0

2
ld/testsuite/ld-aarch64/emit-relocs-271.d
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@ -1,6 +1,6 @@
#source: emit-relocs-271.s
#ld: -T relocs.ld --defsym tempy=0x1012 --defsym tempy2=0x674500 --defsym tempy3=-292 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0

2
ld/testsuite/ld-aarch64/emit-relocs-272.d
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@ -1,6 +1,6 @@
#source: emit-relocs-272.s
#ld: -T relocs.ld --defsym tempy=0x1012 --defsym tempy2=-12345678912345 --defsym tempy3=-292 -e0 --emit-relocs
#objdump: -dr
#objdump: -dr -Mno-aliases
#...
+10000: 8a000000 and x0, x0, x0

13
opcodes/ChangeLog
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@ -1,7 +1,16 @@
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
* aarch64-opc.c (aarch64_print_operand): Change to print
AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
in comment.
* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
OP_MOV_IMM_WIDE.
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>

20
opcodes/aarch64-opc.c
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@ -1,5 +1,5 @@
/* aarch64-opc.c -- AArch64 opcode support.
Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
@ -2433,10 +2433,26 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_IMMR:
case AARCH64_OPND_IMMS:
case AARCH64_OPND_FBITS:
case AARCH64_OPND_IMM_MOV:
snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
break;
case AARCH64_OPND_IMM_MOV:
switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
{
case 4: /* e.g. MOV Wd, #<imm32>. */
{
int imm32 = opnd->imm.value;
snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
}
break;
case 8: /* e.g. MOV Xd, #<imm64>. */
snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
opnd->imm.value, opnd->imm.value);
break;
default: assert (0);
}
break;
case AARCH64_OPND_FPIMM0:
snprintf (buf, size, "#0.0");
break;

8
opcodes/aarch64-tbl.h
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@ -1,6 +1,6 @@
/* aarch64-tbl.h -- AArch64 opcode description table and instruction
operand description table.
Copyright 2012 Free Software Foundation, Inc.
Copyright 2012, 2013 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
@ -2017,7 +2017,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
{"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF},
{"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
{"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_PSEUDO | F_P1 | F_SF | F_CONV},
{"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV},
{"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF},
{"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
{"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF},
@ -2036,9 +2036,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
/* Move wide (immediate). */
{"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
{"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_PSEUDO | F_CONV},
{"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
{"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
{"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_PSEUDO | F_CONV},
{"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
{"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF},
/* PC-rel. addressing. */
{"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0},