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gas/testsuite/
2007-02-11 H.J. Lu <hongjiu.lu@intel.com> PR gas/4027 * gas/i386/opcode.s: Add more tests for "test". * i386/opcode-intel.d: Updated. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. include/opcode/ 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> PR gas/4027 * i386.h (i386_optab): Put the real "test" before the pseudo one.
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@ -1,3 +1,11 @@
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2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/4027
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* gas/i386/opcode.s: Add more tests for "test".
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* i386/opcode-intel.d: Updated.
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* gas/i386/opcode-suffix.d: Likewise.
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* gas/i386/opcode.d: Likewise.
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2007-02-06 Nick Clifton <nickc@redhat.com>
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PR gas/3810 gas/3800
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@ -608,4 +608,8 @@ Disassembly of section .text:
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*[0-9a-f]+: 0f 00 08[ ]+str[ ]+(WORD PTR )?\[eax\]
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*[0-9a-f]+: 0f ad d0 [ ]*shrd[ ]+eax,edx,cl
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*[0-9a-f]+: 0f a5 d0 [ ]*shld[ ]+eax,edx,cl
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*[0-9a-f]+: 85 c3 [ ]*test[ ]+ebx,eax
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*[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx
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*[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx
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#pass
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\.\.\.
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@ -585,4 +585,7 @@ Disassembly of section .text:
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*[0-9a-f]+: 0f 00 08[ ]+strw[ ]+\(%eax\)
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*[0-9a-f]+: 0f ad d0 [ ]*shrdl[ ]+%cl,%edx,%eax
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*[0-9a-f]+: 0f a5 d0 [ ]*shldl[ ]+%cl,%edx,%eax
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\.\.\.
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*[0-9a-f]+: 85 c3 [ ]*testl[ ]+%eax,%ebx
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*[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax
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*[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\)
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#pass
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@ -584,4 +584,7 @@ Disassembly of section .text:
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9ec: 0f 00 08 [ ]*str \(%eax\)
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9ef: 0f ad d0 [ ]*shrd %cl,%edx,%eax
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9f2: 0f a5 d0 [ ]*shld %cl,%edx,%eax
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\.\.\.
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9f5: 85 c3 [ ]*test %eax,%ebx
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9f7: 85 d8 [ ]*test %ebx,%eax
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9f9: 85 18 [ ]*test %ebx,\(%eax\)
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#pass
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@ -581,5 +581,9 @@ foo:
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shrd %cl,%edx,%eax
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shld %cl,%edx,%eax
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test %eax,%ebx
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test %ebx,%eax
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test (%eax),%ebx
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# Force a good alignment.
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.p2align 4,0
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@ -1,3 +1,9 @@
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2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/4027
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* i386.h (i386_optab): Put the real "test" before the pseudo
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one.
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2007-01-08 Kazu Hirata <kazu@codesourcery.com>
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* m68k.h (m68010up): OR fido_a.
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@ -251,8 +251,8 @@ static const template i386_optab[] =
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{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
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{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
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{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
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{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
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{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { AnyMem, Reg, 0} },
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{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
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{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
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