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https://github.com/darlinghq/darling-gdb.git
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2000-07-26 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
* sh-tdep.c (sh_sh4_register_name, sh_sh4_register_byte, sh_sh4_register_raw_size, sh_sh4_register_virtual_type, sh_fetch_pseudo_register, sh_store_pseudo_register, sh_do_pseudo_register, sh_gdbarch_init): Fix names for pseudoregs, they should be numbered as drx fvy where x and y are multiples of 2 and 4 respectively. * config/sh/tm-sh.h: Fix names of pseudo regs.
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510925d36e
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@ -1,3 +1,14 @@
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2000-07-26 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
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* sh-tdep.c (sh_sh4_register_name, sh_sh4_register_byte,
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sh_sh4_register_raw_size, sh_sh4_register_virtual_type,
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sh_fetch_pseudo_register, sh_store_pseudo_register,
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sh_do_pseudo_register, sh_gdbarch_init): Fix names for pseudoregs,
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they should be numbered as drx fvy where x and y are multiples of
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2 and 4 respectively.
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* config/sh/tm-sh.h: Fix names of pseudo regs.
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2000-07-24 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
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* config/sh/tm-sh.h (struct gdbarch_tdep): Add sh4 specific
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@ -44,18 +44,18 @@ struct gdbarch_tdep
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int SPC_REGNUM; /* sh3, sh3-dsp, sh3e, sh4 */
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int RS_REGNUM; /* sh-dsp, sh3-dsp */
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int RE_REGNUM; /* sh-dsp, sh3-dsp */
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int DR0_REGNUM;
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int DR1_REGNUM;
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int DR2_REGNUM;
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int DR3_REGNUM;
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int DR4_REGNUM;
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int DR5_REGNUM;
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int DR6_REGNUM;
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int DR7_REGNUM;
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int FV0_REGNUM;
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int FV1_REGNUM;
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int FV2_REGNUM;
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int FV3_REGNUM;
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int DR0_REGNUM; /* sh4 */
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int DR2_REGNUM; /* sh4 */
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int DR4_REGNUM; /* sh4 */
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int DR6_REGNUM; /* sh4 */
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int DR8_REGNUM; /* sh4 */
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int DR10_REGNUM; /* sh4 */
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int DR12_REGNUM; /* sh4 */
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int DR14_REGNUM; /* sh4 */
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int FV0_REGNUM; /* sh4 */
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int FV4_REGNUM; /* sh4 */
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int FV8_REGNUM; /* sh4 */
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int FV12_REGNUM; /* sh4 */
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};
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/* Registers common to all the SH variants. */
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@ -277,8 +277,8 @@ sh_sh4_register_name (int reg_nr)
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"ssr", "spc",
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"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
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"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
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"dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7",
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"fv0", "fv1", "fv2", "fv3",
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"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
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"fv0", "fv4", "fv8", "fv12",
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};
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if (reg_nr < 0)
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return NULL;
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@ -1440,10 +1440,10 @@ sh_sh4_register_byte (reg_nr)
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int reg_nr;
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{
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if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR7_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
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return (dr_reg_base_num (reg_nr) * 4);
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else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV3_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
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return (fv_reg_base_num (reg_nr) * 4);
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else
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return (reg_nr * 4);
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@ -1463,10 +1463,10 @@ sh_sh4_register_raw_size (reg_nr)
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int reg_nr;
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{
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if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR7_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
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return 8;
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else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV3_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
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return 16;
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else
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return 4;
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@ -1505,10 +1505,10 @@ sh_sh4_register_virtual_type (reg_nr)
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|| (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
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return builtin_type_float;
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else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR7_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
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return builtin_type_double;
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else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV3_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
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return sh_sh4_build_float_register_type (3);
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else
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return builtin_type_int;
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@ -1538,7 +1538,7 @@ sh_fetch_pseudo_register (int reg_nr)
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if (!register_cached (reg_nr))
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{
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if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR7_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
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{
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base_regnum = dr_reg_base_num (reg_nr);
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@ -1548,7 +1548,7 @@ sh_fetch_pseudo_register (int reg_nr)
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target_fetch_registers (base_regnum + portion);
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}
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else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV3_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
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{
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base_regnum = fv_reg_base_num (reg_nr);
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@ -1568,7 +1568,7 @@ sh_store_pseudo_register (int reg_nr)
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int base_regnum, portion;
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if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR7_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
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{
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base_regnum = dr_reg_base_num (reg_nr);
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@ -1580,7 +1580,7 @@ sh_store_pseudo_register (int reg_nr)
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}
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}
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else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV3_REGNUM)
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&& reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
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{
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base_regnum = fv_reg_base_num (reg_nr);
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@ -1645,7 +1645,7 @@ sh_do_pseudo_register (int regnum)
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regnum < gdbarch_tdep (current_gdbarch)->FV0_REGNUM)
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do_dr_register_info (regnum);
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else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM &&
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regnum <= gdbarch_tdep (current_gdbarch)->FV3_REGNUM)
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regnum <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
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do_fv_register_info (regnum);
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}
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@ -1824,17 +1824,17 @@ sh_gdbarch_init (info, arches)
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tdep->SSR_REGNUM = -1;
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tdep->SPC_REGNUM = -1;
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tdep->DR0_REGNUM = -1;
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tdep->DR1_REGNUM = -1;
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tdep->DR2_REGNUM = -1;
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tdep->DR3_REGNUM = -1;
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tdep->DR4_REGNUM = -1;
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tdep->DR5_REGNUM = -1;
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tdep->DR6_REGNUM = -1;
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tdep->DR7_REGNUM = -1;
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tdep->DR8_REGNUM = -1;
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tdep->DR10_REGNUM = -1;
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tdep->DR12_REGNUM = -1;
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tdep->DR14_REGNUM = -1;
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tdep->FV0_REGNUM = -1;
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tdep->FV1_REGNUM = -1;
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tdep->FV2_REGNUM = -1;
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tdep->FV3_REGNUM = -1;
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tdep->FV4_REGNUM = -1;
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tdep->FV8_REGNUM = -1;
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tdep->FV12_REGNUM = -1;
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set_gdbarch_fp0_regnum (gdbarch, -1);
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set_gdbarch_num_pseudo_regs (gdbarch, 0);
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set_gdbarch_max_register_raw_size (gdbarch, 4);
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@ -1959,17 +1959,17 @@ sh_gdbarch_init (info, arches)
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tdep->SSR_REGNUM = 41;
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tdep->SPC_REGNUM = 42;
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tdep->DR0_REGNUM = 59;
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tdep->DR1_REGNUM = 60;
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tdep->DR2_REGNUM = 61;
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tdep->DR3_REGNUM = 62;
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tdep->DR4_REGNUM = 63;
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tdep->DR5_REGNUM = 64;
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tdep->DR6_REGNUM = 65;
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tdep->DR7_REGNUM = 66;
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tdep->DR2_REGNUM = 60;
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tdep->DR4_REGNUM = 61;
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tdep->DR6_REGNUM = 62;
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tdep->DR8_REGNUM = 63;
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tdep->DR10_REGNUM = 64;
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tdep->DR12_REGNUM = 65;
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tdep->DR14_REGNUM = 66;
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tdep->FV0_REGNUM = 67;
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tdep->FV1_REGNUM = 68;
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tdep->FV2_REGNUM = 69;
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tdep->FV3_REGNUM = 70;
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tdep->FV4_REGNUM = 68;
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tdep->FV8_REGNUM = 69;
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tdep->FV12_REGNUM = 70;
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break;
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default:
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sh_register_name = sh_generic_register_name;
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