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* m10300-opc.c: First cut at UDF instructions.
This commit is contained in:
Jeff Law
parent
d826d368a9
commit
ffd95d63ec
@ -1,3 +1,11 @@
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Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com)
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* m10300-opc.c: First cut at UDF instructions.
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Mon Aug 10 14:08:22 1998 Doug Evans <devans@canuck.cygnus.com>
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* m32r-opc.c: Regenerate (remove semantic descriptions).
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start-sanitize-armelf
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Mon Aug 10 12:51:12 1998 Catherine Moore <clm@cygnus.com>
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@ -415,13 +423,13 @@ Mon Jun 1 10:27:26 1998 Jeffrey A Law (law@cygnus.com)
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(sqrt.s): Likewise.
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end-sanitize-r5900
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start-sanitize-vr5400
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start-sanitize-cygnus
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Thu May 28 08:46:09 1998 Catherine Moore <clm@cygnus.com>
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* mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu):
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Change pinfo to use WR_HILO.
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end-sanitize-vr5400
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end-sanitize-cygnus
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Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com>
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* d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b,
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@ -1540,7 +1548,7 @@ Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
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sh-opc.h (sh_table): Remove ftst/nan.
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start-sanitize-vr5400
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start-sanitize-cygnus
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Mon Nov 3 13:23:15 1997 Ken Raeburn <raeburn@cygnus.com>
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* mips-opc.c (dror32, dror, rzu.ob): Fix bugs in encoding.
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@ -1548,7 +1556,7 @@ Mon Nov 3 13:23:15 1997 Ken Raeburn <raeburn@cygnus.com>
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last.
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* mips-dis.c (print_insn_arg): Handle VR5400 operand types.
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end-sanitize-vr5400
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end-sanitize-cygnus
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start-sanitize-tx49
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Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
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@ -1568,10 +1576,10 @@ Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com>
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Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
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* mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
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start-sanitize-vr5400
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start-sanitize-cygnus
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Added VR5400 instructions.
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(N5): New cpu-id macro.
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end-sanitize-vr5400
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end-sanitize-cygnus
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(WR_HILO, RD_HILO, MOD_HILO): New macros.
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Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
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@ -762,7 +762,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
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{ "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
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{ "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
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/* start-sanitize-am33 * /
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/* start-sanitize-am33 */
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{ "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
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/* end-sanitize-am33 */
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{ "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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@ -1031,7 +1031,136 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}},
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{ "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}},
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{ "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}},
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/* { "udf", 0, 0, {0}}, */
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/* UDF instructions. */
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{ "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
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{ "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
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{ "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udf20", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf21", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf22", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf23", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf24", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf25", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf26", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf27", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf28", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf29", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf30", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf31", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf32", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf33", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf34", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udf35", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
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{ "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
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{ "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
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{ "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
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{ "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}},
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{ "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}},
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