* mips-opc.c: Include vu0.h.
* mips-dis.c (print_insn_arg): Handle new args 0-9, +, -, %, K, &,
J, Q, X, and U.
(print_insn_mips): Do not emit a tab after an instruction if the
first arg is an instruction completer (&). If the next arg is an
escape character (%), then print the next arg verbatim.
* Makefile.am (mips-opc.lo): Depend on vu0.h
to *info->symbols.
* mips-dis.c (print_insn_{big,little}_mips): Likewise.
* tic30-dis.c (print_branch): Likewise.
start-sanitize-sky
* mips-dis.c (print_insn_little_mips): Call dvp_info_mach_type.
* dvp-dis.c (dvp_info_mach_type): New function.
(print_insn_dvp): Call it.
(print_vif): Return length of 4 if mpg or direct insn so following
insns get properly disabled.
* dvp-opc.c (vif_insn_len): New argument `pcpu'. All callers updated.
end-sanitize-sky
disassembler.
* mips-dis.c (print_mips16_insn_arg): Display floating point
registers in operands of exit instruction. Print `$' before
register names in operands of entry and exit instructions.
* mips16-opc.c: New file.
* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
(mips16_reg_names): New static array.
(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
after seeing a 16 bit symbol.
(print_insn_little_mips): Likewise.
(print_insn_mips16): New static function.
(print_mips16_insn_arg): New static function.
* mips-opc.c: Add jalx instruction.
* Makefile.in (mips16-opc.o): New target.
* configure.in: Use mips16-opc.o for bfd_mips_arch.
* configure: Rebuild.
than s,t. Change div macro to be d,v,t rather than d,s,t.
Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu,
rem and remu which generates only the corresponding div
instruction. This is for compatibility with the MIPS assembler,
which only generates the simple machine instruction when an
explicit destination of $0 is used.
* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
