Add D8 for 8-bit unsigned field in short load/store insns.
(IF4A, IF4D): These both need two registers.
(IF4C, IF4D): Define. Use 8-bit unsigned field.
(v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
for "ldsr" and "stsr".
* v850-opc.c (v850_operands): 3-bit immediate for bit insns
is unsigned.
Fixing up the parser again.
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
memory transfer instructions. Add new format string entries %h and %s.
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
(print_insn_alpha_vms): Remove.
(print_insn_alpha): Make globally visible. Chose the register
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
* d10v-opc.c: Changes to support signed and unsigned numbers.
All instructions with the same name that have long and short forms
now end in ".l" or ".s". Divs added.
* d10v-dis.c: Changes to support signed and unsigned numbers.
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
end-sanitize-d10v
* alpha-dis.c (print_insn_alpha): No longer the user-visible
print routine. Take new regnames and cpumask arguments.
Kill the environment variable nonsense.
(print_insn_alpha_osf): New function. Do OSF/1 style regnames.
(print_insn_alpha_vms): New function. Do VMS style regnames.
* disassemble.c (disassembler): Test bfd flavour to pick
between OSF and VMS routines. Default to OSF.
the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
* alpha-opc.c: New file.
* alpha-opc.h: Remove.
* alpha-dis.c: Complete rewrite to use new opcode table.
* configure.in: For bfd_alpha_arch, use alpha-opc.o.
* configure: Rebuild with autoconf 2.10.
* Makefile.in (ALL_MACHINES): Add alpha-opc.o.
(alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not
alpha-opc.h.
(alpha-opc.o): New target.
to just "mode".
start-sanitize-h8s
* disassemble.c (disassembler): Handle H8/S.
* h8300-dis.c (print_insn_h8300s): New function for H8/S.
end-sanitize-h8s
Even more H8/S goo.
not "abs", which may be needed for the absolute in something
like btst #0,@10:8. Print L_3 immediates separately from other
immediates. Change ABSMOV reference to ABS8MEM.
One day we'll actually disassemble btst #0,@10:8 correctly... But not
yet. hmse.
(current_arch_mask): New static global.
(compute_arch_mask): New static function.
(print_insn_sparc): Delete sparc_v9_p. New static local
current_mach. Resort opcode table if current_mach changes.
Generalize "insn not supported" test.
(compare_opcodes): Prefer supported opcodes to nonsupported ones.
Delete test for v9/!v9.
* sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
(v6notlet): Define.
(brfc): Split into CBR and FBR for coprocessor/fp branches.
(brfcx): Renamed to FBRX.
(condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard
coprocessor mnemonics are not supported on the sparclet).
(condf): Renamed to CONDF.
(SLCBCC2): Delete F_ALIAS flag.
* configure: Rebuild.
* Makefile.in (SHLIB_DEP): New variable.
(LIBIBERTY_LISTS, BFD_LIST): New variables.
(stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If
COMMON_SHLIB, add them to piclist with appropriate modifications.
($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB
here: just use piclist.
* i386-dis.c (onebyte_has_modrm): New static array.
(twobyte_has_modrm): New static array.
(print_insn_i386): Only fetch the mod/reg/rm byte if it is needed.
(reg): Add HX instructions.
start-sanitize-i960xl
The HX instructions are the XL instructions, so this just involves
arranges for them to not be sanitized.
end-sanitize-i960xl
Alan Modra <alan@spri.levels.unisa.edu.au>:
* configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib.
New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC,
SHLIB_CFLAGS, COMMON_SHLIB, SHLINK.
* configure: Rebuild.
* Makefile.in (ALLLIBS): New variable.
(PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables.
(COMMON_SHLIB, SHLINK): New variables.
(.c.o): If PICFLAG is set, compile twice, once PIC, once normal.
(STAGESTUFF): Remove variable.
(all): Depend upon $(ALLLIBS) rather than $(TARGETLIB).
(stamp-piclist, piclist): New targets.
($(SHLIB), $(SHLINK)): New targets.
($(OFILES)): Depend upon stamp-picdir.
(disassemble.o): Build twice if PICFLAG is set.
(MOSTLYCLEAN): Add pic/*.o.
(clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist.
(distclean): Remove pic and stamp-picdir.
(install): Install shared libraries.
(stamp-picdir): New target.
If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode
architecture.
(print_insn_sparc64): Deleted.
* disassemble.c (disassembler, case bfd_arch_sparc): Always use
print_insn_sparc.
* alpha-opc.h (alpha_insn_set): VAX floating point opcode was
incorrectly defined as 0x16 when it should be 0x15.
(FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits!
(alpha_insn_set): added cvtst and cvttq float ops. Also added
excb (exception barrier) which is defined in the Alpha
Architecture Handbook version 2.
* alpha-dis.c (print_insn_alpha): Fixed special-case decoding for
OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be
disassembled as or, for example.
* m68k-dis.c (NEXTSINGLE): Change i to unsigned int.
(NEXTDOUBLE): Likewise.
(print_insn_m68k): Don't match fmoveml if there is more than one
register in the list.
(print_insn_arg): Handle a place of '8' for a type of 'L'.
* m68k-dis.c (print_insn_m68k): Recognize all two-word instructions that take
no args by looking at the match mask.
(print_insn_arg): Always print "%" before register names.
[case 'c']: Use "nc" for the no-cache case, as recognized by gas.
[case '_']: Don't print "@#" before address.
[case 'J']: Use "%s" as format string, not register name.
[case 'B']: Treat place == 'C' like 'l' and 'L'.
* alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added.
(alpha_insn_set): added definitions for VAX floating point
instructions (Unix compilers don't generate these, but handcoded
assembly might still use them).
* alpha-dis.c (print_insn_alpha): added support for disassembling
the miscellaneous instructions in the Alpha instruction set.
no longer create sysdep.h, sed ppc-opc.c to work around a
serious Metrowerks C bug.
* mpw-make.in: Remove.
* mpw-make.sed: New file, used by mpw-configure to edit
Makefile.in into an MPW makefile.
which use '0', '1', and '2' instead. Specify the proper size for
a pmove immediate operand. Correct the pmovefd patterns to be
moves to a register, not from a register.
* m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'.
Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute
host_makefile_frag or frags.
* aclocal.m4: New file.
* configure: Rebuild.
* Makefile.in (INSTALL): Set to @INSTALL@.
(INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@.
(INSTALL_DATA): Set to @INSTALL_DATA@.
(AR): Set to @AR@.
(AR_FLAGS): Set to rc rather than qc.
(CC): Define as @CC@.
(CFLAGS): Set to @CFLAGS@.
(@host_makefile_frag@): Remove.
(config.status): Remove dependency upon @frags@.
(reg_names): Likewise.
(print_insn_arg): Don't explicitly print % before register names.
Add % before register names in static array names. In case 'r',
print data registers as `@(Dn)', not `Dn@'. When printing a
memory address, don't print @# before it.
(print_indexed): Change base_disp and outer_disp from int to
bfd_vma. Print using MIT syntax, not mutant invalid Motorola
syntax. Sign extend 8 byte displacement correctly.
(print_base): Print using MIT syntax. Print zpc when appropriate.
Change parameter disp from int to bfd_vma.
F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N.
* sh-opc.h (sh_arg_type): Add new operand types.
(sh_table): Add new opcodes from SH3E Floating Point ISA.
sh3e stuff. Sanitized out for now.
Clean up tables.
* m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff.
(opcode): Remove.
(print_insn_m68k): Change d to be const. Use m68k_numopcodes
rather than numopcodes. Use m68k_opcodes rather than removed
opcode function. Don't check F_ALIAS.
(print_insn_arg): Change first parameter to be const char *.
* Makefile.in (ALL_MACHINES): Add m68k-opc.o.
(m68k-opc.o): New target.
* configure.in: Build m68k-opc.o for bfd_m68k_arch.
* configure: Rebuild.
(opcode_bits, opcode_hash_table, sparc64_p): New variables.
(opcodes_initialized): Renamed from opcodes_sorted.
(build_hash_table): New function.
(is_delayed_branch): Use hash table.
(print_insn): Renamed from print_insn_sparc, made static.
Build and use hash table.
(print_insn_sparc, print_insn_sparc64): New functions.
(compare_opcodes): If !sparc64, move sparc64 opcodes to end,
and vice-versa if sparc64.
* sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS.
* mips-opc.c (L1): Define.
(mips_opcodes): Add R4010 instructions: flushi, flushd, flushid,
addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti,
and wb.
Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com>
* mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
if ISA 3 and addu otherwise, replacing or, since some MIPS chips
have multiple add units but only a single logical unit.
bfd_vma to unsigned long, because _print_insn_mips expects an unsigned long,
and that might be fewer words of argument storage (e.g., if bfd_vma is long
long on a 32-bit machine).
(print_insn_big_mips): Likewise with bfd_getb32 value.
(_print_insn_mips): Now static.
Call arc_get_opcode_mach to map bfd mach number to opcode value.
(print_insn_*): Pass bfd mach number, not opcode version.
* arc-opc.c (arc_get_opcode_mach): New function.
* alpha-opc.h (OSF_ASMCODE): define print pal-code names as defined in App C of
the Alpha Architecture Reference Manual
* alpha-dis.c: cleaned up output print stylized code forms as defined in App
A.4.3 of the Alpha Architecture Reference Manual
(print_insn_arc_{host,graphics,audio}): Likewise.
(print_insn): Add prototype.
Delete "+ 4" addition to relative branch address.
(arc_get_disassembler): New arg `big_p'. Return little or big
print fn accordingly.
* arc-opc.c (arc_opcode_init_tables): Init arc_operand_map once.
(arc_opcode_supported): Use ARC_OPCODE_CPU to ignore byte order.
(arc_opval_supported): Likewise.
* disassemble.c (disassembler): Pass big endian flag to
arc_get_disassembler.
(UNSIGNED, SATURATION): New operands.
(mac, mul, mul64, mulu64): New insns.
(ext. asl, asr, lsr, ror): Only available on host and graphics cpus.
(padc, padd, pmov, pand, psbc, psub, swap): New insns.
(host,graphics,audio extended and auxiliary regs): Define.
(ss, sc, mh, ml): New suffixes.
(arc_opcode_supported, arc_opval_supported): New functions.
(insert_multshift, extract_multshift): Deleted.
New argument `cpu', pass it to arc_opcode_init_tables.
Document byte order dependencies. Ignore unsupported insns.
(arc_disassembler): New function.
(print_insn_arc_base, print_insn_arc_host, print_insn_arc_graphics,
print_insn_arc_audio): New functions.
<edelsohn@npac.syr.edu>.
(powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of
SPR.
(FXM_MASK): Define.
(insert_tbr): New static function.
(extract_tbr): New static function.
(XFXFXM_MASK, XFXM): Define.
(XSPRBAT_MASK, XSPRG_MASK): Define.
(powerpc_opcodes): Add instructions to access special registers by
name. Add mtcr and mftbu.
