gold/
PR ld/20995
* copy-relocs.cc (Copy_relocs::make_copy_reloc): Use .dynbss for
read-only data when linking with -z relro.
* copy-relocs.h (Copy_relocs::dynrelro_): New data member.
* testsuite/Makefile.am (copy_test_relro): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/copy_test_relro.cc: New source file.
* testsuite/copy_test_relro_1.cc: New source file.
Variables defined in shared libraries are copied into an executable's
.bss section when code in the executable is non-PIC and thus would
require dynamic text relocations to access the variable directly in
the shared library. Recent x86 toolchains also copy variables into
the executable to gain a small speed improvement.
The problem is that if the variable was originally read-only, the copy
in .bss is writable, potentially opening a security hole. This patch
cures that problem by putting the copy in a section that becomes
read-only after ld.so relocation, provided -z relro is in force.
The patch also fixes a microblaze linker segfault on attempting to
use dynamic bss variables.
bfd/
PR ld/20995
* elf-bfd.h (struct elf_link_hash_table): Add sdynrelro and
sreldynrelro.
(struct elf_backend_data): Add want_dynrelro.
* elfxx-target.h (elf_backend_want_dynrelro): Define.
(elfNN_bed): Update initializer.
* elflink.c (_bfd_elf_create_dynamic_sections): Create
sdynrelro and sreldynrelro sections.
* elf32-arm.c (elf32_arm_adjust_dynamic_symbol): Place variables
copied into the executable from read-only sections into sdynrelro.
(elf32_arm_size_dynamic_sections): Handle sdynrelro.
(elf32_arm_finish_dynamic_symbol): Select sreldynrelro for
dynamic relocs in sdynrelro.
(elf_backend_want_dynrelro): Define.
* elf32-hppa.c (elf32_hppa_adjust_dynamic_symbol)
(elf32_hppa_size_dynamic_sections, elf32_hppa_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-i386.c (elf_i386_adjust_dynamic_symbol)
(elf_i386_size_dynamic_sections, elf_i386_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-metag.c (elf_metag_adjust_dynamic_symbol)
(elf_metag_size_dynamic_sections, elf_metag_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-microblaze.c (microblaze_elf_adjust_dynamic_symbol)
(microblaze_elf_size_dynamic_sections)
(microblaze_elf_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-nios2.c (nios2_elf32_finish_dynamic_symbol)
(nios2_elf32_adjust_dynamic_symbol)
(nios2_elf32_size_dynamic_sections)
(elf_backend_want_dynrelro): As above.
* elf32-or1k.c (or1k_elf_finish_dynamic_symbol)
(or1k_elf_adjust_dynamic_symbol, or1k_elf_size_dynamic_sections)
(elf_backend_want_dynrelro): As above.
* elf32-ppc.c (ppc_elf_adjust_dynamic_symbol)
(ppc_elf_size_dynamic_sections, ppc_elf_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-s390.c (elf_s390_adjust_dynamic_symbol)
(elf_s390_size_dynamic_sections, elf_s390_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-tic6x.c (elf32_tic6x_adjust_dynamic_symbol)
(elf32_tic6x_size_dynamic_sections)
(elf32_tic6x_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf32-tilepro.c (tilepro_elf_adjust_dynamic_symbol)
(tilepro_elf_size_dynamic_sections)
(tilepro_elf_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf64-ppc.c (ppc64_elf_adjust_dynamic_symbol)
(ppc64_elf_size_dynamic_sections, ppc64_elf_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf64-s390.c (elf_s390_adjust_dynamic_symbol)
(elf_s390_size_dynamic_sections, elf_s390_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elf64-x86-64.c (elf_x86_64_adjust_dynamic_symbol)
(elf_x86_64_size_dynamic_sections)
(elf_x86_64_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elfnn-aarch64.c (elfNN_aarch64_adjust_dynamic_symbol)
(elfNN_aarch64_size_dynamic_sections)
(elfNN_aarch64_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elfnn-riscv.c (riscv_elf_adjust_dynamic_symbol)
(riscv_elf_size_dynamic_sections, riscv_elf_finish_dynamic_symbol)
(elf_backend_want_dynrelro): As above.
* elfxx-mips.c (_bfd_mips_elf_adjust_dynamic_symbol)
(_bfd_mips_elf_size_dynamic_sections)
(_bfd_mips_vxworks_finish_dynamic_symbol): As above.
* elfxx-sparc.c (_bfd_sparc_elf_adjust_dynamic_symbol)
(_bfd_sparc_elf_size_dynamic_sections)
(_bfd_sparc_elf_finish_dynamic_symbol): As above.
* elfxx-tilegx.c (tilegx_elf_adjust_dynamic_symbol)
(tilegx_elf_size_dynamic_sections)
(tilegx_elf_finish_dynamic_symbol): As above.
* elf32-mips.c (elf_backend_want_dynrelro): Define.
* elf64-mips.c (elf_backend_want_dynrelro): Define.
* elf32-sparc.c (elf_backend_want_dynrelro): Define.
* elf64-sparc.c (elf_backend_want_dynrelro): Define.
* elf32-tilegx.c (elf_backend_want_dynrelro): Define.
* elf64-tilegx.c (elf_backend_want_dynrelro): Define.
* elf32-microblaze.c (microblaze_elf_adjust_dynamic_symbol): Tidy.
(microblaze_elf_size_dynamic_sections): Handle sdynbss.
* elf32-nios2.c (nios2_elf32_size_dynamic_sections): Make use
of linker shortcuts to dynamic sections rather than comparing
names. Correctly set "got" flag.
ld/
PR ld/20995
* testsuite/ld-arm/farcall-mixed-app-v5.d: Update to suit changed
stub hash table traversal caused by section id increment. Accept
the previous output too.
* testsuite/ld-arm/farcall-mixed-app.d: Likewise.
* testsuite/ld-arm/farcall-mixed-lib-v4t.d: Likewise.
* testsuite/ld-arm/farcall-mixed-lib.d: Likewise.
* testsuite/ld-elf/pr20995a.s, * testsuite/ld-elf/pr20995b.s,
* testsuite/ld-elf/pr20995.r: New test.
* testsuite/ld-elf/elf.exp: Run it.
The only target that renames .bss is tic6x, turning .bss into .far,
and .sbss into .bss. .dynbss is not renamed to .dynfar by BFD.
* scripttempl/elf.sc: Don't use $BSS_NAME in .dynbss.
Revert commit 17733f5be9 ("Increment the ABIVERSION to 5 for MIPS
objects with non-executable stacks.") and remove EI_ABIVERSION 5
allocation for PT_GNU_STACK support, which has not made it to glibc
and will be reassigned.
bfd/
* bfd/elfxx-mips.c (_bfd_mips_post_process_headers): Revert
2016-02-23 change and remove EI_ABIVERSION 5 support.
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Simplify extended operand handling and only specially process immediates
which require bit shuffling, using the generic operand insertion and
extraction handlers for the '<' (5-bit shift amount) operand code in
particular. Require the least significant bit of all extended operand
forms to be (artificially) set to 0 for their special processing to
trigger.
gas/
* config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend'
use to operands whose LSB position is zero.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Simplify processing of
extended operands.
* mips16-opc.c (decode_mips16_operand): Switch the extended
form of the `<' operand type to LSB position 22.
Bail out right away when an unextended instruction encoding is required
either with the use of a `.t' suffix or by means of `.set noautoextend',
however an operand supplied requires the extended instruction form to be
used.
This is to avoid messing up with the internal state of the assembler,
even though no actual failures are known to happen as a result. Add
test cases for the situation concerned.
gas/
* config/tc-mips.c (match_mips16_insn): Don't update
`forced_insn_length' or the instruction opcode if an operand
requires an extended instruction form, but an unextended one
has been requested.
* testsuite/gas/mips/mips16-relax-unextended-1.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-2.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-relax-unextended-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range. No functional change.
gas/
* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_macro): Likewise.
include/
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
opcodes/
* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_opcodes): Likewise.
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Remove special casing for the `6' operand code used for the embedded
trap code of the BREAK and the SDBBP instructions to support supposedly
extended forms of these instructions.
According to all versions of the MIPS16 ASE specifications these
instructions are not extensible [1][2][3][4][5][7][8][10][11], and as
from revision 2.50 of the MIPS16e ASE specifications it has been further
clarified what was previously implied, that non-extesiable instructions
when preceded with an EXTEND prefix must cause a Reserved Instruction
exception [5][6][9][10].
Therefore supposedly extended BREAK and SDBBP instructions do not serve
their purpose anymore as they do not cause a Bp and a Debug exception
respectively and supporting these forms in disassembly only causes
confusion.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] same, Table 18. "Extendable MIPS16 Instructions", p. 24
[4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38
[5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41
[6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41
[7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49
[8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39
[9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42
[10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43
[11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50
gas/
* config/tc-mips.c (match_mips16_insn): Remove the `6' operand
code special case and its associated comment.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
encoding support.
Correct the handling of `.e' and `.t' instruction size suffixes with
instruction mnemonics which are not followed by any text on the same
line, such as arguments or white space, e.g.:
$ cat test.s
.set mips16
foo:
entry.t # comment
entry.t
exit.t # comment
exit.t
nop.t # comment
nop.t
$ as -32 -o test.o test.s
test.s: Assembler messages:
test.s:4: Error: unrecognized opcode `entry.t'
test.s:6: Error: unrecognized opcode `exit.t'
test.s:8: Error: unrecognized opcode `nop.t'
$
gas/
* config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction
suffixes followed by a null character rather than a space too.
* testsuite/gas/mips/mips16-insn-length-noargs.d: New test.
* testsuite/gas/mips/mips16-insn-length-noargs.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new test.
Do not allow any explicitly coded EXTEND instruction to be automatically
scheduled into a jump delay slot, as an EXTEND prefix is coupled with
the next regular MIPS16 instruction and therefore swapping it with a
jump would change program's semantics; EXTEND is not architecturally
allowed to be present in a jump delay slot anyway.
opcodes/
* mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
"extend".
gas/
* testsuite/gas/mips/mips16-extend-swap.d: New test.
* testsuite/gas/mips/mips16-extend-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Fix a regression introduced with commit 5e7fc731f8 ("MIPS/opcodes:
Also set disassembler's ASE flags from ELF structures"), further updated
with commit 4df995c771 ("MIPS/opcodes: Also set disassembler's ASE
flags from ELF structures"), and use autoconf to check for the presence
of `bfd_mips_elf_get_abiflags' in BFD.
opcodes/
* mips-dis.c (set_default_mips_dis_options): Use
HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
call to `bfd_mips_elf_get_abiflags'.
* configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
* aclocal.m4: Regenerate.
* configure: Regenerate.
* config.in: Regenerate.
* Makefile.in: Regenerate.
This allows targets that have target specific code to add object
symbols to make use of the generic archive handling.
* linker.c (generic_link_check_archive_element): Call target
bfd_link_add_symbols to add element symbols.
Nothing calls them and they were in the way of a bug fix.
* linker.c (generic_link_add_symbols): Delete. Merge into..
(_bfd_generic_link_add_symbols): ..here.
(generic_link_check_archive_element_no_collect): Delete.
(generic_link_check_archive_element_collect): Likewise.
(generic_link_add_object_symbols): Remove "collect" param. Update
callers.
(generic_link_add_symbol_list): Likewise.
(generic_link_check_archive_element): Likewise. Call
bfd_link_add_symbols rather than generic_link_add_object_symbols.
* libbfd-in.h (_bfd_generic_link_add_symbols_collect): Delete.
* libbfd.h: Regenerate.
This stops an --enable-targets selection affecting the main target in
regards to forcing 64-bit archives. It also means mips64 and s390x
will revert to binutils-2.25 and binutils-2.26 behaviour of not
forcing 64-bit archives at least in the common case when plugins were
enabled.
PR binutils/20464
PR binutils/14625
* configure.ac: Revert 2016-05-25 configure change setting
want_64_bit_archive for mips64 and s390x. Revise USE_64_BIT_ARCHIVE
description.
* configure: Regenerate.
* config.in: Regenerate.
This patch syncs the generated data structure in tc-msp430.c with the
latest version of devices.csv released by TI.
My understanding is that the devices being removed were "invalid spins",
so can't be being used by anyone, and never will be. Current web
searches related to these devices return no relevant results.
Built and tested (no regressions) as follows:
Configured with: --target=msp430-elf --disable-gdb
Test variations:
msp430-sim/-mcpu=msp430
msp430-sim/-mcpu=msp430x
msp430-sim/-mcpu=msp430x/-mlarge/-mdata-region=either/-mcode-region=either
msp430-sim/-mhwmult=none
msp430-sim/-mhwmult=f5series
gas/
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
devices.csv file as of September 2016.
gold/
PR gold/17643
* options.h (-z bndplt): New option.
* x86_64.cc (Output_data_plt_x86_64::regular_count): New method.
(Output_data_plt_x86_64::address_for_global): Move implementation into
virtual method.
(Output_data_plt_x86_64::address_for_local): Likewise.
(Output_data_plt_x86_64::got): New method.
(Output_data_plt_x86_64::got_plt): New method.
(Output_data_plt_x86_64::got_irelative): New method.
(Output_data_plt_x86_64::do_address_for_global): New virtual method.
(Output_data_plt_x86_64::do_address_for_local): New virtual method.
(class Output_data_plt_x86_64_bnd): New class.
(Target_x86_64::do_make_data_plt): Move out of line and specialize
for each size (both overloads).
(Output_data_plt_x86_64::set_final_data_size): Cosmetic changes.
* testsuite/Makefile.am (bnd_plt_1): New test case.
(bnd_ifunc_1): New test case.
(bnd_ifunc_2): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/bnd_ifunc_1.s: New source file.
* testsuite/bnd_ifunc_1.sh: New shell script.
* testsuite/bnd_ifunc_2.s: New source file.
* testsuite/bnd_ifunc_2.sh: New shell script.
* testsuite/bnd_plt_1.s: New source file.
* testsuite/bnd_plt_1.sh: New shell script.
Gold was not placing forced-local symbols (e.g., hidden visibility)
at the front of the dynamic symbol table, or including them in the
count of local symbols recorded in the .dynsym section's sh_info field.
gold/
* layout.cc (Layout::finalize): Track count of forced-local symbols
in .dynsym.
(Layout::create_symtab_sections): Add local_dynamic_count parameter;
use that instead of sh_info value.
(Layout::create_dynamic_symtab): Add pforced_local_dynamic_count
parameter; pass it to Symtab::set_dynsym_indexes(). Include forced
locals in sh_info value. Pass index of first real global to
Dynobj::create_gnu_hash_table() and Dynobj::create_elf_hash_table().
* layout.h (Layout::create_symtab_sections): Add local_dynamic_count
parameter.
(Layout::create_dynamic_symtab): Add pforced_local_dynamic_count
parameter.
* symtab.cc (Symbol_table::set_dynsym_indexes): Add pforced_local_count
parameter. Process forced-local symbols first and return the count.
(Symbol_table::finalize): Update comments.
* symtab.h (Symbol_table::set_dynsym_indexes): Add pforced_local_count
parameter.
(Symbol_table::first_dynamic_global_index_): Update comment.
(Symbol_table::dynamic_count_): Update comment.
* testsuite/Makefile.am (ifuncmod1.sh): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/ifuncmod1.sh: New shell script.
When creating a predefined hidden symbol like _GLOBAL_OFFSET_TABLE_, gold
was incorrectly letting a version script add a version to the symbol,
resulting in two copies of the symbol, both STB_LOCAL, but one of which
was grouped in the globals part of the symbol table.
gold/
* symtab.cc (Symbol_table::define_special_symbol): Add is_forced_local
parameter; if set, do not check version script.
(Symbol_table::do_define_in_output_data): Pass is_forced_local for
STB_LOCAL predefined symbols.
(Symbol_table::do_define_in_output_segment): Likewise.
(Symbol_table::do_define_in_output_segment): Likewise.
(Symbol_table::do_define_as_constant): Likewise.
* symtab.h (Symbol_table::define_special_symbol): Add is_forced_local
parameter. Adjust all callers.
* testsuite/Makefile.am (ver_test_8.sh): New test case.
* testsuite/Makefile.in: Regenerate.
* ver_test_8.sh: New test script.
We don't want to report a test failure as a tcl error.
* testsuite/ld-scripts/sysroot-prefix.exp (sysroot_prefix_test_setup):
Call perror rather than error on "as" or "ar" failures.
Linker-created symbols like __ehdr_start, __etext, __edata, and end
should be relocatable, not absolute.
gold/
* output.cc (Output_segment::first_section): Return NULL if there are
no sections in the segment.
* output.h (Output_segment::first_section_load_address): Assert that
first section is not NULL.
* symtab.cc (Symbol_table::sized_write_globals): Attach linker-created
segment-relative symbols to first section of the segment.
Contrary to the comment, they can in fact be called.
* libbfd-in.h (_bfd_vms_lib_slurp_armap): Use _bfd_noarchive function.
(_bfd_vms_lib_slurp_extended_name_table: Likewise.
(_bfd_vms_lib_construct_extended_name_table: Likewise.
(_bfd_vms_lib_truncate_arname: Likewise.
(_bfd_vms_lib_write_armap: Likewise.
(_bfd_vms_lib_read_ar_hdr: Likewise.
(_bfd_vms_lib_write_ar_hdr: Likewise.
* libbfd.h: Regenerate.
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd). Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.
Resolves https://github.com/riscv/riscv-gnu-toolchain/issues/205
* config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
(riscv_frag_align_code): Correct frag_align_code arg.
Instructions like "jal t0, foo" were erroneously creating symbol table
entries for t0 as well as foo, which causes linking problems. Fix by
reordering instruction alternatives so that t0 is first attempted to
be parsed as a register, rather than as a symbol.
* riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
ILP32 has 32-bit word and address, but currently they declared as 64-bit in
bfd_aarch64_arch_ilp32, which breaks further logic of bfd. This patch fixes it.
Glibc testsuite build with patched binutils shows that next tests stop to fail:
iconvdata/mtrace-tst-loading
iconvdata/tst-loading
iconvdata/tst-tables
localedata/mtrace-tst-leaks
localedata/tst-leaks
posix/tst-getaddrinfo4
posix/tst-getaddrinfo5
posix/tst-regex2
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
