Commit Graph

6 Commits

Author SHA1 Message Date
Ian Lance Taylor
9978cd4dc9 * mips-opc.c: Correct lwu opcode value (book had it wrong). 1993-10-05 21:49:04 +00:00
Ian Lance Taylor
547998d2c8 * mips-opc.c: Change div machine instruction to be z,s,t rather
than s,t.  Change div macro to be d,v,t rather than d,s,t.
	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
	rem and remu which generates only the corresponding div
	instruction.  This is for compatibility with the MIPS assembler,
	which only generates the simple machine instruction when an
	explicit destination of $0 is used.
	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
1993-09-02 17:14:10 +00:00
Ian Lance Taylor
a9c686adf5 * mips-opc.c: Move div machine instruction after macro forms.
Change d,s,t form to d,v,t.  Likewise for divu, ddiv and ddivu.
	This is for compatibility with the MIPS assembler, which only
	generates the simple machine instruction when an explicit
	destination of $0 is used.
1993-09-02 14:42:31 +00:00
Ian Lance Taylor
a5ba0d3f48 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set
WR_31 hazard for bal, bgezal, bltzal.
1993-08-27 14:55:22 +00:00
Ian Lance Taylor
2bef2d3e57 * mips-opc.c: Added r6000 and r4000 instructions and macros.
Changed hazard information to distinguish between memory load
	delays and coprocessor load delays.
1993-08-20 15:40:51 +00:00
Ian Lance Taylor
45b1470513 * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. 1993-08-18 19:40:37 +00:00