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fa6761106f
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358 Commits

Author SHA1 Message Date
Jeff Law
fa6761106f Arggh. B3. shift counts are from the start of each half-word apparently. 1996-08-22 02:20:08 +00:00
Jeff Law
4cd595fcdd Fix thinko in B3. 1996-08-22 02:18:07 +00:00
Jeff Law
7c8157dd48 * v850-opc.c (v850_operands): Add "B3" support. 
(v850_opcodes): Fix and enable "set1", "clr1", "not1"
        and "tst1".
 1996-08-22 02:08:02 +00:00
Jeff Law
fed1d21fc0 * v850-ope.c ("jmp"): R1 is only operand. 1996-08-22 01:39:22 +00:00
Jeff Law
b10e29f4b8 * v850-opc.c: Close unterminated comment. 
Something -Wall caught.
 1996-08-22 00:46:47 +00:00
J.T. Conklin
6bc33c7fa5 * v850-opc.c: Add flags field to struct v850_operands, add move 
opcodes to opcode table.
 1996-08-22 00:35:28 +00:00
J.T. Conklin
6d1e1ee875 * Makefile.in (ALL_MACHINES): Add v850-opc.o. 
* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
 1996-08-20 21:45:02 +00:00
David Edelsohn
5751b0d72d * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. 1996-08-19 22:22:11 +00:00
Stan Shebs
a952ea1cb8 * mpw-make.sed: Update editing of include pathnames to be 
more general.
 1996-08-15 20:13:38 +00:00
Jackie Smith Cashion
5247a22a88 Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> 
* arm-opc.h: Added "bx" instruction definition.
 1996-08-15 15:29:41 +00:00
Ian Lance Taylor
375d76efcc Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> 
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
 1996-08-15 00:01:21 +00:00
Martin Hunt
ed36b6cd33 Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
 1996-08-12 21:32:03 +00:00
Martin Hunt
cff827d7df Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
 1996-08-09 20:25:12 +00:00
Ian Lance Taylor
0f38eaa09f Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> 
* makefile.vms: Update for alpha-opc changes.
 1996-08-08 16:45:05 +00:00
Ian Lance Taylor
484c464505 * i386-dis.c (print_insn_i386): Actually return the correct value. 
(ONE, OP_ONE): #ifdef out; not used.
 1996-08-07 15:56:13 +00:00
Martin Hunt
c5e1996f55 Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
	Changed subi operand type to treat 0 as 16.
 1996-08-03 00:49:00 +00:00
Ian Lance Taylor
82e8213e4e * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose 
<rose@netcom.com>.
 1996-07-31 20:22:50 +00:00
Jackie Smith Cashion
50569deeb5 Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> 
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
 	memory transfer instructions. Add new format string entries %h and %s.
	* arm-dis.c: (print_insn_arm): Provide decoding of the new
	formats %h and %s.
 1996-07-31 13:43:51 +00:00
Martin Hunt
3dd5a8d337 Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
 	(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
 1996-07-26 18:59:21 +00:00
Ian Lance Taylor
239ce44d9c * alpha-dis.c (print_insn_alpha_osf): Remove. 
(print_insn_alpha_vms): Remove.
	(print_insn_alpha): Make globally visible.  Chose the register
	names based on info->flavour.
	* disassemble.c: Always return print_insn_alpha for the alpha.
 1996-07-26 18:06:35 +00:00
Martin Hunt
ab0a229408 Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-dis.c (dis_long): Handle unknown opcodes.
 1996-07-25 22:28:10 +00:00
Martin Hunt
0be715623f Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c: Changes to support signed and unsigned numbers.
	All instructions with the same name that have long and short forms
	now end in ".l" or ".s".  Divs added.
	* d10v-dis.c: Changes to support signed and unsigned numbers.
 1996-07-25 19:16:34 +00:00
Martin Hunt
687c3cc863 start-sanitize-d10v 
Tue Jul 23 11:02:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>

	* d10v-dis.c: Change all functions to use info->print_address_func.

end-sanitize-d10v
 1996-07-23 18:11:55 +00:00
Ian Lance Taylor
354447a435 Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
 	move ccr/sr insns more strict so that the disassembler only
 	selects them when the addressing mode is data register.
 1996-07-22 19:49:24 +00:00
Martin Hunt
95e3e73328 start-sanitize-d10v 
Mon Jul 22 11:25:24 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
        * d10v-opc.c (pre_defined_registers):  Declare.
        * d10v-dis.c (print_operand): Now uses pre_defined_registers
        to pick a better name for the registers.

end-sanitize-d10v
 1996-07-22 18:57:20 +00:00
Ian Lance Taylor
d82a4ac0aa fix last patch 1996-07-22 18:38:50 +00:00
Ian Lance Taylor
e4024966b2 * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix 
operands for fexpand and fpmerge.  From Christian Kuehnke
	<Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>.
 1996-07-22 17:58:19 +00:00
Ian Lance Taylor
e7bc7bc3fc Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> 
* alpha-dis.c (print_insn_alpha): No longer the user-visible
	print routine.  Take new regnames and cpumask arguments.
	Kill the environment variable nonsense.
	(print_insn_alpha_osf): New function.  Do OSF/1 style regnames.
	(print_insn_alpha_vms): New function.  Do VMS style regnames.
	* disassemble.c (disassembler): Test bfd flavour to pick
	between OSF and VMS routines.  Default to OSF.
 1996-07-22 17:19:09 +00:00
Ian Lance Taylor
8ec904659e * configure.in: Call AC_SUBST (INSTALL_SHLIB). 
* configure: Rebuild.
	* Makefile.in (install): Use @INSTALL_SHLIB@.
 1996-07-18 21:20:15 +00:00
Martin Hunt
e3659cbf49 start-sanitize-d10v 
Wed Jul 17 14:39:05 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
        * configure: (bfd_d10v_arch) Add new case.
        * configure.in: (bfd_d10v_arch) Add new case.
        * d10v-dis.c: New file.
        * d10v-opc.c: New file.
        * disassemble.c (disassembler) Add entry for d10v.
end-sanitize-d10v
 1996-07-18 00:49:26 +00:00
J.T. Conklin
dec678d6ca Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> 
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
        to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
 1996-07-17 17:18:13 +00:00
Stu Grossman
9498be1a05 oops! 1996-07-16 00:03:38 +00:00
Stu Grossman
d9ad578c49 * i386-dis.c (print_insn_i8086): New routine to disassemble using 
the 8086 instruction set.
	* i386-dis.c:  General cleanups.  Make most things static.  Add
	prototypes.  Get rid of static variables aflags and dflags.  Pass
	them as args (to almost everything).
 1996-07-16 00:01:50 +00:00
Stu Grossman
be0c8b0508 * i386-dis.c (print_insn_i8086): New routine to disassemble using 
the 8086 instruction set.
	* i386-dis.c:  General cleanups.  Make most things static.  Add
	prototypes.  Get rid of static variables aflags and dflags.  Pass
	them as args (to almost everything).
 1996-07-12 17:15:38 +00:00
Jeff Law
3b2a7894d8 * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. 
More HMSE.
 1996-07-11 19:06:21 +00:00
Jeff Law
8e9c1f74c9 * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". 
More disassembler fixes.  HMSE.
 1996-07-11 18:59:57 +00:00
Jeff Law
52aa53362e * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two 
if the next arg is marked with SRC_IN_DST.  Gross.
Gross hack so that shift-by-two insns are disassembled correctly.
 1996-07-11 18:46:41 +00:00
Jeff Law
b3ef936e6b * h8300-dis.c (bfd_h8_disassemble): Print "exr" when 
we're looking for and find EXR.
So we disassemble andc/orc/xorc with exr correctly.
 1996-07-11 18:30:02 +00:00
Jeff Law
81fc72a71a * h8300-dis.c (bfd_h8_disassemble): We don't have a match 
if we're looking for KBIT and we don't find it.
So we don't disassemble "inc" instructions as "adds" instructions.
 1996-07-11 18:24:59 +00:00
Jeff Law
bf0b880f39 * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits 
for L_3 and L_2.
So we only get values in the right range for L_3 (0..7) and L_2 (0..3).
 1996-07-11 18:07:31 +00:00
Jeff Law
0decb7fde3 * h8300-dis.c (bfd_h8_disassemble): Don't set plen for 
3bit immediate operands.
So we disassemble bXXX #IMM,@ADDRESS insns correctly.
 1996-07-11 17:58:43 +00:00
Ian Lance Taylor
1695403700 * alpha-opc.c: Add new case of "mov". From Klaus Kaempf 
<kkaempf@progis.ac-net.de>.
 1996-07-09 14:57:34 +00:00
Jeff Law
25b344a4a2 No longer need to sanitize away h8s stuff. 1996-07-05 18:59:31 +00:00
Ian Lance Taylor
972b1bb03e * alpha-opc.c: Correct second case of "mov" to use OPRL. 1996-07-04 15:43:31 +00:00
Stu Grossman
eb2c851803 * sparc-dis.c (print_insn_sparclite): New routine to print 
sparclite instructions.
 1996-07-04 00:50:29 +00:00
J.T. Conklin
9070eaffef * m68k-opc.c (m68k_opcodes): Add coldfire support. 1996-07-03 21:28:05 +00:00
David Edelsohn
b1dd184ef7 * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, 
#ASI_NUCLEUS_LITTLE.  Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L
	to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE.
 1996-06-28 22:56:17 +00:00
Jason Molenda
2f70f660a6 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): 
Use autoconf-set values.
        (docdir, oldincludedir): Removed.
        * configure.in (AC_PREREQ): autoconf 2.5 or higher.
 1996-06-25 14:00:47 +00:00
Ian Lance Taylor
96926bf0f6 Fri Jun 21 13:53:36 1996 Richard Henderson <rth@tamu.edu> 
* alpha-opc.c: New file.
	* alpha-opc.h: Remove.
	* alpha-dis.c: Complete rewrite to use new opcode table.
	* configure.in: For bfd_alpha_arch, use alpha-opc.o.
	* configure: Rebuild with autoconf 2.10.
	* Makefile.in (ALL_MACHINES): Add alpha-opc.o.
	(alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not
	alpha-opc.h.
	(alpha-opc.o): New target.
 1996-06-21 17:58:07 +00:00
Ian Lance Taylor
4264a46e65 * sparc-dis.c (print_insn_sparc): Remove unused local variable i. 
Set imm_added_to_rs1 even if the source and destination register
	are not the same.
 1996-06-20 01:18:47 +00:00