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6ced10dd55
the lower 32-bit halves of the GPRS to be their own raw registers, not pseudoregisters. * ppc-tdep.h (struct gdbarch_tdep): Remove ppc_gprs_pseudo_p flag; add ppc_ev0_upper_regnum flag. * rs6000-tdep.c: #include "reggroups.h". (spe_register_p): Recognize the ev upper half registers as SPE registers. (init_sim_regno_table): Build gdb->sim mappings for the upper-half registers. (e500_move_ev_register): New function. (e500_pseudo_register_read, e500_pseudo_register_write): The 'ev' vector registers are the pseudo-registers now, formed by splicing together the gprs and the upper-half registers. (e500_register_reggroup_p): New function. (P): Macro deleted. (P8, A4): New macro. (PPC_EV_REGS, PPC_GPRS_PSEUDO_REGS): Macros deleted. (PPC_SPE_GP_REGS, PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): New macros. (registers_e500): Rearrange register set so that the raw register set contains 32-bit GPRs and upper-half registers, and the SPE vector registers become pseudo-registers. (rs6000_gdbarch_init): Don't initialize tdep->ppc_gprs_pseudo_p; it has been deleted. Initialize ppc_ev0_upper_regnum. Many other register numbers are now the same for the E500 as they are for other PowerPC variants. Register e500_register_reggroup_p as the register group function for the E500. * Makefile.in (rs6000-tdep.o): Update dependencies. Adapt PPC E500 native support to the new raw regcache layout. * ppc-linux-nat.c (struct gdb_evrregset_t): Doc fixes. (read_spliced_spe_reg, write_spliced_spe_reg): Deleted. (fetch_spe_register, store_spe_register): Handle fetching/storing all the SPE registers at once, if regno == -1. These now take over the job of fetch_spe_registers and store_spe_registers. (fetch_spe_registers, store_spe_registers): Deleted. (fetch_ppc_registers, store_ppc_registers): Fetch/store gprs unconditionally; they're always raw. Fetch/store SPE upper half registers, if present, instead of ev registers. (fetch_register, store_register): Remove sanity checks: gprs are never pseudo-registers now, so we never need to even mention any registers that are ever pseudoregisters.
377 lines
12 KiB
C
377 lines
12 KiB
C
/* Target-dependent code for GDB, the GNU debugger.
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Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation,
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Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#ifndef PPC_TDEP_H
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#define PPC_TDEP_H
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struct gdbarch;
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struct frame_info;
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struct value;
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struct regcache;
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struct type;
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/* From ppc-linux-tdep.c... */
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enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
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struct type *valtype,
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struct regcache *regcache,
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void *readbuf,
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const void *writebuf);
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enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
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struct type *valtype,
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struct regcache *regcache,
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void *readbuf,
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const void *writebuf);
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CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
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struct value *function,
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struct regcache *regcache,
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CORE_ADDR bp_addr, int nargs,
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struct value **args, CORE_ADDR sp,
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int struct_return,
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CORE_ADDR struct_addr);
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CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
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struct value *function,
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struct regcache *regcache,
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CORE_ADDR bp_addr, int nargs,
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struct value **args, CORE_ADDR sp,
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int struct_return,
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CORE_ADDR struct_addr);
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CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
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CORE_ADDR bpaddr);
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int ppc_linux_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache);
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struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
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void ppc_linux_supply_gregset (struct regcache *regcache,
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int regnum, const void *gregs, size_t size,
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int wordsize);
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void ppc_linux_supply_fpregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *gregs, size_t size);
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enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
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struct type *valtype,
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struct regcache *regcache,
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void *readbuf,
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const void *writebuf);
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/* From rs6000-tdep.c... */
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int altivec_register_p (int regno);
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int spe_register_p (int regno);
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/* Return non-zero if the architecture described by GDBARCH has
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floating-point registers (f0 --- f31 and fpscr). */
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int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
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/* Register set description. */
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struct ppc_reg_offsets
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{
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/* General-purpose registers. */
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int r0_offset;
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int pc_offset;
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int ps_offset;
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int cr_offset;
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int lr_offset;
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int ctr_offset;
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int xer_offset;
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int mq_offset;
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/* Floating-point registers. */
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int f0_offset;
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int fpscr_offset;
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/* AltiVec registers. */
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int vr0_offset;
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int vscr_offset;
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int vrsave_offset;
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};
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/* Supply register REGNUM in the general-purpose register set REGSET
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from the buffer specified by GREGS and LEN to register cache
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REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
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extern void ppc_supply_gregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *gregs, size_t len);
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/* Supply register REGNUM in the floating-point register set REGSET
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from the buffer specified by FPREGS and LEN to register cache
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REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
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extern void ppc_supply_fpregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *fpregs, size_t len);
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/* Collect register REGNUM in the general-purpose register set
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REGSET. from register cache REGCACHE into the buffer specified by
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GREGS and LEN. If REGNUM is -1, do this for all registers in
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REGSET. */
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extern void ppc_collect_gregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *gregs, size_t len);
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/* Collect register REGNUM in the floating-point register set
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REGSET. from register cache REGCACHE into the buffer specified by
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FPREGS and LEN. If REGNUM is -1, do this for all registers in
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REGSET. */
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extern void ppc_collect_fpregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *fpregs, size_t len);
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/* Private data that this module attaches to struct gdbarch. */
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struct gdbarch_tdep
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{
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int wordsize; /* size in bytes of fixed-point word */
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const struct reg *regs; /* from current variant */
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int ppc_gp0_regnum; /* GPR register 0 */
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int ppc_toc_regnum; /* TOC register */
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int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
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int ppc_cr_regnum; /* Condition register */
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int ppc_lr_regnum; /* Link register */
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int ppc_ctr_regnum; /* Count register */
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int ppc_xer_regnum; /* Integer exception register */
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/* On PPC and RS6000 variants that have no floating-point
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registers, the next two members will be -1. */
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int ppc_fp0_regnum; /* floating-point register 0 */
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int ppc_fpscr_regnum; /* Floating point status and condition
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register */
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int ppc_sr0_regnum; /* segment register 0, or -1 on
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variants that have no segment
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registers. */
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int ppc_mq_regnum; /* Multiply/Divide extension register */
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int ppc_vr0_regnum; /* First AltiVec register */
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int ppc_vrsave_regnum; /* Last AltiVec register */
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int ppc_ev0_upper_regnum; /* First GPR upper half register */
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int ppc_ev0_regnum; /* First ev register */
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int ppc_ev31_regnum; /* Last ev register */
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int ppc_acc_regnum; /* SPE 'acc' register */
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int ppc_spefscr_regnum; /* SPE 'spefscr' register */
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int lr_frame_offset; /* Offset to ABI specific location where
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link register is saved. */
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/* An array of integers, such that sim_regno[I] is the simulator
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register number for GDB register number I, or -1 if the
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simulator does not implement that register. */
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int *sim_regno;
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};
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/* Constants for register set sizes. */
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enum
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{
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ppc_num_gprs = 32, /* 32 general-purpose registers */
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ppc_num_fprs = 32, /* 32 floating-point registers */
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ppc_num_srs = 16, /* 16 segment registers */
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ppc_num_vrs = 32 /* 32 Altivec vector registers */
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};
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/* Constants for SPR register numbers. These are *not* GDB register
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numbers: they are the numbers used in the PowerPC ISA itself to
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refer to these registers.
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This table includes all the SPRs from all the variants I could find
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documentation for.
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There may be registers from different PowerPC variants assigned the
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same number, but that's fine: GDB and the SIM always use the
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numbers in the context of a particular variant, so it's not
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ambiguous.
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We need to deviate from the naming pattern when variants have
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special-purpose registers of the same name, but with different
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numbers. Fortunately, this is rare: look below to see how we
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handle the 'tcr' registers on the 403/403GX and 602. */
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enum
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{
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ppc_spr_mq = 0,
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ppc_spr_xer = 1,
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ppc_spr_rtcu = 4,
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ppc_spr_rtcl = 5,
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ppc_spr_lr = 8,
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ppc_spr_ctr = 9,
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ppc_spr_cnt = 9,
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ppc_spr_dsisr = 18,
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ppc_spr_dar = 19,
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ppc_spr_dec = 22,
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ppc_spr_sdr1 = 25,
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ppc_spr_srr0 = 26,
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ppc_spr_srr1 = 27,
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ppc_spr_eie = 80,
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ppc_spr_eid = 81,
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ppc_spr_nri = 82,
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ppc_spr_sp = 102,
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ppc_spr_cmpa = 144,
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ppc_spr_cmpb = 145,
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ppc_spr_cmpc = 146,
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ppc_spr_cmpd = 147,
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ppc_spr_icr = 148,
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ppc_spr_der = 149,
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ppc_spr_counta = 150,
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ppc_spr_countb = 151,
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ppc_spr_cmpe = 152,
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ppc_spr_cmpf = 153,
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ppc_spr_cmpg = 154,
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ppc_spr_cmph = 155,
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ppc_spr_lctrl1 = 156,
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ppc_spr_lctrl2 = 157,
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ppc_spr_ictrl = 158,
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ppc_spr_bar = 159,
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ppc_spr_vrsave = 256,
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ppc_spr_sprg0 = 272,
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ppc_spr_sprg1 = 273,
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ppc_spr_sprg2 = 274,
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ppc_spr_sprg3 = 275,
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ppc_spr_asr = 280,
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ppc_spr_ear = 282,
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ppc_spr_tbl = 284,
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ppc_spr_tbu = 285,
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ppc_spr_pvr = 287,
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ppc_spr_spefscr = 512,
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ppc_spr_ibat0u = 528,
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ppc_spr_ibat0l = 529,
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ppc_spr_ibat1u = 530,
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ppc_spr_ibat1l = 531,
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ppc_spr_ibat2u = 532,
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ppc_spr_ibat2l = 533,
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ppc_spr_ibat3u = 534,
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ppc_spr_ibat3l = 535,
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ppc_spr_dbat0u = 536,
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ppc_spr_dbat0l = 537,
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ppc_spr_dbat1u = 538,
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ppc_spr_dbat1l = 539,
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ppc_spr_dbat2u = 540,
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ppc_spr_dbat2l = 541,
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ppc_spr_dbat3u = 542,
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ppc_spr_dbat3l = 543,
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ppc_spr_ic_cst = 560,
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ppc_spr_ic_adr = 561,
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ppc_spr_ic_dat = 562,
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ppc_spr_dc_cst = 568,
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ppc_spr_dc_adr = 569,
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ppc_spr_dc_dat = 570,
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ppc_spr_dpdr = 630,
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ppc_spr_dpir = 631,
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ppc_spr_immr = 638,
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ppc_spr_mi_ctr = 784,
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ppc_spr_mi_ap = 786,
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ppc_spr_mi_epn = 787,
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ppc_spr_mi_twc = 789,
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ppc_spr_mi_rpn = 790,
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ppc_spr_mi_cam = 816,
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ppc_spr_mi_ram0 = 817,
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ppc_spr_mi_ram1 = 818,
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ppc_spr_md_ctr = 792,
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ppc_spr_m_casid = 793,
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ppc_spr_md_ap = 794,
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ppc_spr_md_epn = 795,
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ppc_spr_m_twb = 796,
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ppc_spr_md_twc = 797,
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ppc_spr_md_rpn = 798,
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ppc_spr_m_tw = 799,
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ppc_spr_mi_dbcam = 816,
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ppc_spr_mi_dbram0 = 817,
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ppc_spr_mi_dbram1 = 818,
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ppc_spr_md_dbcam = 824,
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ppc_spr_md_cam = 824,
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ppc_spr_md_dbram0 = 825,
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ppc_spr_md_ram0 = 825,
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ppc_spr_md_dbram1 = 826,
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ppc_spr_md_ram1 = 826,
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ppc_spr_ummcr0 = 936,
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ppc_spr_upmc1 = 937,
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ppc_spr_upmc2 = 938,
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ppc_spr_usia = 939,
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ppc_spr_ummcr1 = 940,
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ppc_spr_upmc3 = 941,
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ppc_spr_upmc4 = 942,
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ppc_spr_zpr = 944,
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ppc_spr_pid = 945,
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ppc_spr_mmcr0 = 952,
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ppc_spr_pmc1 = 953,
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ppc_spr_sgr = 953,
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ppc_spr_pmc2 = 954,
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ppc_spr_dcwr = 954,
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ppc_spr_sia = 955,
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ppc_spr_mmcr1 = 956,
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ppc_spr_pmc3 = 957,
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ppc_spr_pmc4 = 958,
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ppc_spr_sda = 959,
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ppc_spr_tbhu = 972,
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ppc_spr_tblu = 973,
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ppc_spr_dmiss = 976,
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ppc_spr_dcmp = 977,
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ppc_spr_hash1 = 978,
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ppc_spr_hash2 = 979,
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ppc_spr_icdbdr = 979,
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ppc_spr_imiss = 980,
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ppc_spr_esr = 980,
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ppc_spr_icmp = 981,
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ppc_spr_dear = 981,
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ppc_spr_rpa = 982,
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ppc_spr_evpr = 982,
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ppc_spr_cdbcr = 983,
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ppc_spr_tsr = 984,
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ppc_spr_602_tcr = 984,
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ppc_spr_403_tcr = 986,
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ppc_spr_ibr = 986,
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ppc_spr_pit = 987,
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ppc_spr_esasrr = 988,
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ppc_spr_tbhi = 988,
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ppc_spr_tblo = 989,
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ppc_spr_srr2 = 990,
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ppc_spr_sebr = 990,
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ppc_spr_srr3 = 991,
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ppc_spr_ser = 991,
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ppc_spr_hid0 = 1008,
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ppc_spr_dbsr = 1008,
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ppc_spr_hid1 = 1009,
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ppc_spr_iabr = 1010,
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ppc_spr_dbcr = 1010,
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ppc_spr_iac1 = 1012,
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ppc_spr_dabr = 1013,
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ppc_spr_iac2 = 1013,
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ppc_spr_dac1 = 1014,
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ppc_spr_dac2 = 1015,
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ppc_spr_l2cr = 1017,
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ppc_spr_dccr = 1018,
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ppc_spr_ictc = 1019,
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ppc_spr_iccr = 1019,
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ppc_spr_thrm1 = 1020,
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ppc_spr_pbl1 = 1020,
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ppc_spr_thrm2 = 1021,
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ppc_spr_pbu1 = 1021,
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ppc_spr_thrm3 = 1022,
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ppc_spr_pbl2 = 1022,
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ppc_spr_fpecr = 1022,
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ppc_spr_lt = 1022,
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ppc_spr_pir = 1023,
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ppc_spr_pbu2 = 1023
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};
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#endif
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